公开(公告)号：US20250151265A1

公开(公告)日：2025-05-08

申请号：US18740568

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongman Park ,  Sungho Jang ,  Seungho Hong ,  Jeonghoon Oh

IPC: H10B12/00

Abstract: An integrated circuit device includes gate structures arranged on an upper surface of a substrate, a first impurity region arranged at the upper surface of the substrate, wherein the first impurity region is adjacent to a first gate structure of the gate structures, a first contact pad arranged on the upper surface of the substrate, wherein the first contact pad comprises a recess recessed in a vertical direction perpendicular to the upper surface of the substrate from an upper surface of the first contact pad toward the upper surface of the substrate, a metal silicide layer disposed in the recess, and a contact via connected to the metal silicide layer and extending in the vertical direction. A lower end of the contact via is disposed in the recess and connected to the metal silicide layer. The contact via is spaced apart from the substrate in the vertical direction.