公开(公告)号：US09484409B2

公开(公告)日：2016-11-01

申请号：US14846176

申请日：2015-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Sun Lee ,  Junhwa Song ,  Ji Hun Kim ,  Jeonghoon Oh

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/10 ,  H01L29/08 ,  H01L29/04 ,  H01L27/11 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/412

CPC classification number: H01L29/1033 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1079

Abstract: A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type. The source/drain regions have a second conductivity type. A concentration of dopants having the first conductivity type in the channel dopant layer is higher than a concentration of dopants having the first conductivity type in the channel region. The semiconductor device may be used in a sense amplifier of a memory device.

Abstract translation: 一种半导体器件包括：半导体衬底，包括具有第一导电类型的阱掺杂剂层，阱掺杂剂层上的栅极电极，阱掺杂剂层中的沟道掺杂剂层，并且与半导体衬底的顶表面间隔开;沟道 栅电极和沟道掺杂剂层之间的区域以及栅电极两侧的阱掺杂剂层中的源/漏区。 沟道掺杂剂层和沟道区具有第一导电类型。 源极/漏极区域具有第二导电类型。 在沟道掺杂剂层中具有第一导电类型的掺杂剂的浓度高于沟道区中具有第一导电类型的掺杂剂的浓度。 半导体器件可以用在存储器件的读出放大器中。

公开(公告)号：US09842841B2

公开(公告)日：2017-12-12

申请号：US14849651

申请日：2015-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hun Kim ,  Ilgweon Kim ,  Junhwa Song ,  Jeonghoon Oh ,  WonSeok Yoo ,  Eun-Sun Lee

IPC: H01L21/8242 ,  H01L21/762 ,  H01L21/311 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/8238 ,  H01L49/02

CPC classification number: H01L27/10894 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10891 ,  H01L28/91

Abstract: A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a device isolation trench; forming a device isolation layer defining active regions by sequentially stacking a first insulating layer, a second insulating layer, and a third insulating layer on an inner surface of the device isolation trench; forming word lines buried in the substrate of the first region, the word lines extending in a first direction to intersect the active region of the first region, the word lines being spaced apart from each other; forming a first mask layer covering the word lines on the substrate of the first region, the first mask layer exposing the substrate of the second region; forming a channel layer on the substrate of the second region; and forming a gate electrode on the channel layer.

公开(公告)号：US20240072175A1

公开(公告)日：2024-02-29

申请号：US18300579

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhwa Song ,  Changsik Kim ,  Jaewon Na ,  Deokhwan Choi

IPC: H01L29/786 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H01L29/78642 ,  H10B12/315

Abstract: A semiconductor device includes an upper conductive line on a substrate, a channel structure adjacent the upper conductive line, a gate dielectric film between the channel structure and the upper conductive line, and a conductive contact pattern electrically connected to the channel structure. The channel structure includes a main channel portion including an oxide semiconductor layer having a first composition, and a channel contact portion between the main channel portion and the conductive contact pattern. The channel contact portion is in contact with the conductive contact pattern and includes a material having a second composition that is different from the first composition.