SENSOR FOR ACCUMULATION SIGNAL
    2.
    发明申请

    公开(公告)号:US20200260033A1

    公开(公告)日:2020-08-13

    申请号:US16584148

    申请日:2019-09-26

    Abstract: A sensor includes a determining circuit and an output circuit. The determining circuit receives a first signal from a pixel in response to light and outputs a second signal associated with occurrence of an event, based on the first signal. Based on the second signal being received in a time period between a first time when a third signal is received from a processor and a second time when a condition is satisfied, the output circuit outputs a fourth signal associated with occurrence of the event in the time period to the processor after the second time.

    Flash memory device and computing device including flash memory cells

    公开(公告)号:US11270759B2

    公开(公告)日:2022-03-08

    申请号:US17006990

    申请日:2020-08-31

    Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell region including first metal pads and a memory cell array; and a peripheral circuit region including a second metal pads and vertically connected to the memory cell region by the first metal pads and the second metal pads directly. The peripheral circuit region includes a row decoder block; a buffer block storing a command and an address received from an external semiconductor chip through the first pads; a page buffer block connected to the memory cell array through bit lines, connected to the third pads through data lines, and exchanging data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block receiving control signals from the external semiconductor chip through the second pads, and controlling the row decoder block and the page buffer block.

    Image sensor including CMOS image sensor pixel and dynamic vision sensor pixel

    公开(公告)号:US11637983B2

    公开(公告)日:2023-04-25

    申请号:US17492059

    申请日:2021-10-01

    Abstract: An image sensor includes a CIS (CMOS image sensor) pixel, a DVS (dynamic vision sensor) pixel, and an image signal processor. The CIS pixel includes a photoelectric conversion device generating charges corresponding to an incident light and a readout circuit generating an output voltage corresponding to the generated charges. The DVS pixel detects a change in an intensity of the incident light based on the generated charges to output an event signal and does not include a separate photoelectric conversion device. The image signal processor allows the photoelectric conversion device to be connected to the readout circuit or the DVS pixel.

    Sensor for accumulation signal
    8.
    发明授权

    公开(公告)号:US11558573B2

    公开(公告)日:2023-01-17

    申请号:US16584148

    申请日:2019-09-26

    Abstract: A sensor includes a determining circuit and an output circuit. The determining circuit receives a first signal from a pixel in response to light and outputs a second signal associated with occurrence of an event, based on the first signal. Based on the second signal being received in a time period between a first time when a third signal is received from a processor and a second time when a condition is satisfied, the output circuit outputs a fourth signal associated with occurrence of the event in the time period to the processor after the second time.

    Flash memory device and computing device including flash memory cells

    公开(公告)号:US11264084B2

    公开(公告)日:2022-03-01

    申请号:US16871815

    申请日:2020-05-11

    Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.

    FLASH MEMORY DEVICE AND COMPUTING DEVICE INCLUDING FLASH MEMORY CELLS

    公开(公告)号:US20210118488A1

    公开(公告)日:2021-04-22

    申请号:US17006990

    申请日:2020-08-31

    Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell region including first metal pads and a memory cell array; and a peripheral circuit region including a second metal pads and vertically connected to the memory cell region by the first metal pads and the second metal pads directly. The peripheral circuit region includes a row decoder block; a buffer block storing a command and an address received from an external semiconductor chip through the first pads; a page buffer block connected to the memory cell array through bit lines, connected to the third pads through data lines, and exchanging data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block receiving control signals from the external semiconductor chip through the second pads, and controlling the row decoder block and the page buffer block.

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