公开(公告)号：US11329044B2

公开(公告)日：2022-05-10

申请号：US16951260

申请日：2020-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-sik Shin ,  Heung-sik Park ,  Do-haing Lee ,  In-keun Lee ,  Seung-ho Chae ,  Ha-young Choi

IPC: H01L27/092 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: An integrated circuit device is provided. The integrated circuit device includes a fin-type active region that extends in a first direction on a substrate, a gate structure that intersects with the fin-type active region and extends in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure that is disposed on the gate structure, and has a greater width at a top surface than a bottom surface thereof.

公开(公告)号：US20200075596A1

公开(公告)日：2020-03-05

申请号：US16443349

申请日：2019-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-sik Shin ,  Heung-sik Park ,  Do-haing Lee ,  In-keun Lee ,  Seung-ho Chae ,  Ha-young Choi

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: An integrated circuit device includes a fin-type active region extending in a first direction parallel on a substrate, a gate structure intersecting with the fin-type active region and extending in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure disposed on the gate structure, an having a greater width at a top surface than a bottom surface thereof.

公开(公告)号：US20180211952A1

公开(公告)日：2018-07-26

申请号：US15850243

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-sik Shin ,  Do-hyoung Kim ,  Doo-young Lee ,  Hyon-wook Ra ,  Seo-bum Lee ,  Won-hyuk Lee

IPC: H01L27/06 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/5283 ,  H01L23/53295 ,  H01L28/24 ,  H01L29/785

Abstract: Provided is a semiconductor device having an enhanced characteristic and a resistor structure satisfying a desired target resistor value of a resistor device. A semiconductor device includes: a lower interlayer insulating layer disposed on a substrate comprising a resistor area; a resistor structure comprising a resistor layer and an etch stop pattern sequentially stacked on the lower interlayer insulating layer of the resistor area; an upper interlayer insulating layer configured to cover the resistor structure and disposed on the lower interlayer insulating layer; a resistor contact structure configured to pass through the upper interlayer insulating layer and the etch stop pattern and contact the resistor layer; and a resistor contact spacer disposed between the upper interlayer insulating layer, the etch stop pattern, and the resistor contact structure.

公开(公告)号：US11776962B2

公开(公告)日：2023-10-03

申请号：US17715192

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-sik Shin ,  Heung-sik Park ,  Do-haing Lee ,  In-keun Lee ,  Seung-ho Chae ,  Ha-young Choi

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/12

Abstract: An integrated circuit device is provided. The integrated circuit device includes a fin-type active region that extends in a first direction on a substrate, a gate structure that intersects with the fin-type active region and extends in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure that is disposed on the gate structure, and has a greater width at a top surface than a bottom surface thereof.

公开(公告)号：US11114535B2

公开(公告)日：2021-09-07

申请号：US16152956

申请日：2018-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-yoon Ahn ,  Sang-hyun Lee ,  Sung-woo Kang ,  Hong-sik Shin ,  Seong-han Oh ,  Young-mook Oh ,  In-keun Lee

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/033 ,  H01L27/088 ,  H01L29/165 ,  H01L29/45 ,  H01L21/768 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08

Abstract: A semiconductor device may include a substrate including a fin active region extending in a first direction, a gate structure crossing the fin active region and extending in a second direction crossing the first direction, source/drain regions on the fin active region at opposite sides of the gate structure, a first contact structure electrically connected to one of the source/drain regions, a pair of first contact block structures on opposite first sidewalls, respectively, of the first contact structure in the second direction.

公开(公告)号：US20190305098A1

公开(公告)日：2019-10-03

申请号：US16152956

申请日：2018-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-yoon Ahn ,  Sang-hyun Lee ,  Sung-woo Kang ,  Hong-sik Shin ,  Seong-han Oh ,  Young-mook Oh ,  In-keun Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device may include a substrate including a fin active region extending in a first direction, a gate structure crossing the fin active region and extending in a second direction crossing the first direction, source/drain regions on the fin active region at opposite sides of the gate structure, a first contact structure electrically connected to one of the source/drain regions, a pair of first contact block structures on opposite first sidewalls, respectively, of the first contact structure in the second direction.

公开(公告)号：US10381345B2

公开(公告)日：2019-08-13

申请号：US15850243

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-sik Shin ,  Do-hyoung Kim ,  Doo-young Lee ,  Hyon-wook Ra ,  Seo-bum Lee ,  Won-hyuk Lee

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Provided is a semiconductor device having an enhanced characteristic and a resistor structure satisfying a desired target resistor value of a resistor device. A semiconductor device includes: a lower interlayer insulating layer disposed on a substrate comprising a resistor area; a resistor structure comprising a resistor layer and an etch stop pattern sequentially stacked on the lower interlayer insulating layer of the resistor area; an upper interlayer insulating layer configured to cover the resistor structure and disposed on the lower interlayer insulating layer; a resistor contact structure configured to pass through the upper interlayer insulating layer and the etch stop pattern and contact the resistor layer; and a resistor contact spacer disposed between the upper interlayer insulating layer, the etch stop pattern, and the resistor contact structure.