公开(公告)号：US09859432B2

公开(公告)日：2018-01-02

申请号：US15245549

申请日：2016-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsun Ko ,  Sangjine Park ,  Hagju Cho ,  Byungjae Park ,  Jeongnam Han

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device may include a pair of active patterns spaced apart from each other in a first direction, a pair of gate electrodes intersecting the pair of the active patterns in a second direction crossing the first direction, gate spacers on sidewalls of the pair of the active patterns, source/drain regions on the pair active patterns between the pair of the gate electrodes, and a spacer protection pattern between the pair of the gate electrodes and between the pair of the active patterns. The spacer protection pattern may be commonly connected to the gate spacers.

公开(公告)号：US20150108584A1

公开(公告)日：2015-04-23

申请号：US14582429

申请日：2014-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yangsoo Son ,  Hyerim Moon ,  Hagju Cho ,  Jeongnam Han ,  Joon Goo Hong

IPC: H01L27/11 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823462 ,  H01L27/0207 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/517 ,  H01L29/7848

Abstract: A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners.

Abstract translation: 半导体器件包括限定第一有源区的第一器件隔离图案，限定第二有源区的第二器件隔离图案，设置在第一有源区上的第一栅极，第一栅极包括第一厚度的栅极绝缘图案和 第二栅极，其设置在第二有源区上，第二栅极包括具有大于第一厚度的第二厚度的栅极绝缘图案。 第一器件隔离图案的顶表面朝向第一有源区域向下弯曲，使得第一有源区域具有从顶表面和圆角突出的上部。

公开(公告)号：US12302635B2

公开(公告)日：2025-05-13

申请号：US18486331

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi Cho ,  Sangdeok Kwon ,  Dae Sin Kim ,  Dongwon Kim ,  Yonghee Park ,  Hagju Cho

IPC: H10D84/90 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D89/10

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US09627481B2

公开(公告)日：2017-04-18

申请号：US15051056

申请日：2016-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungjae Park ,  Myeongcheol Kim ,  Hagju Cho

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/7854 ,  H01L29/7856

Abstract: A semiconductor device includes a multi-fin active region having a plurality of sub-fins sequentially arranged on a substrate. A gate electrode crosses the multi-fin active region. Source/drain regions are disposed on the sub-fins except a first sub-fin and a last sub-fin. A contact plug is disposed on the source/drain regions.

公开(公告)号：US20240030326A1

公开(公告)日：2024-01-25

申请号：US18159200

申请日：2023-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sora YOU ,  Kyoungwoo Lee ,  Sungmoon Lee ,  Seungmin Cha ,  Hagju Cho

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/0673

Abstract: A semiconductor device includes parallel active regions on a substrate and extending in a first horizontal direction; gate structures intersecting the active regions, extending in a second horizontal direction, and including first and second gate structures opposing each other in the second horizontal direction; source/drain regions including first and second source/drain regions, on at least one side of the gate structures and on the active regions; a gate separation pattern between the first and second gate structures; a vertical conductive structure in the gate separation pattern; contact plugs including a first contact plug electrically connected to the first source/drain region and the vertical conductive structure, and a second contact plug electrically connected to the second source/drain region and spaced apart from the vertical conductive structure; and a contact separation pattern separating the first and second contact plugs, having a portion contacting an upper surface of the vertical conductive structure.

公开(公告)号：US11824059B2

公开(公告)日：2023-11-21

申请号：US17369236

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi Cho ,  Sangdeok Kwon ,  Dae Sin Kim ,  Dongwon Kim ,  Yonghee Park ,  Hagju Cho

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/82385 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L2027/11829 ,  H01L2027/11851 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20130149835A1

公开(公告)日：2013-06-13

申请号：US13690456

申请日：2012-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangsoo Son ,  Hyerim Moon ,  Hagju Cho ,  Jeongnam Han ,  Joon Goo Hong

IPC: H01L29/40

CPC classification number: H01L27/1104 ,  H01L21/823462 ,  H01L27/0207 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/517 ,  H01L29/7848

Abstract: A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners.