公开(公告)号：US20150162247A1

公开(公告)日：2015-06-11

申请号：US14531987

申请日：2014-11-03

Applicant: SAMSUNG ELECTRONICS CO., Ltd.

Inventor： Yong-Joon CHOI ,  MYEONGCHEOL KIM ,  CHEOL KIM ,  GeumJung SEONG ,  Hak-Sun LEE ,  Haegeon JUNG ,  Ji-Eun HAN

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/0886

Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Abstract translation: 本公开提供半导体器件及其制造方法。 该方法包括使用形成在衬底上的第一掩模图案来蚀刻衬底以形成沟槽，形成填充沟槽的初步器件隔离图案，并且包括具有第一厚度的第一和第二区域，在第一区域上形成第二掩模图案，蚀刻 第二区域的上部和第一掩模图案的一部分被第二掩模图案曝光，以形成具有小于第一厚度的第二厚度的第二区域，去除第一和第二掩模图案，以及蚀刻 所述第一区域的上部和所述第二区域具有第二厚度，以形成限定预备鳍型活性图案的器件隔离图案。 还公开了一种包括半导体器件及其制造方法的电子器件。

公开(公告)号：US20250142952A1

公开(公告)日：2025-05-01

申请号：US18796895

申请日：2024-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haegeon JUNG ,  Dongkwon Kim ,  Myeongji Kim ,  Sangduk Park ,  Keunhee Bai ,  Gahyun Lim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L25/18 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of manufacturing an integrated circuit device is provided. The method includes: providing a substrate including a base substrate layer, an insulating substrate layer, and a cover substrate layer that are sequentially stacked in a vertical direction; forming, on the substrate, a stacked structure including a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers that are alternately stacked one layer at a time; and forming a plurality of trench regions to define a plurality of fin-type active regions by etching the stacked structure and the substrate. The he forming of the plurality of trench regions includes, by using the insulating substrate layer as an etch stop layer, etching portions of the stacked structure and the cover substrate layer in the vertical direction up to an upper surface of the insulating substrate layer.

公开(公告)号：US20170162674A1

公开(公告)日：2017-06-08

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Kyung Yub JEON ,  Sujin JUNG ,  Haegeon JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US20220189970A1

公开(公告)日：2022-06-16

申请号：US17392377

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haegeon JUNG ,  Taeyong KWON ,  Kwang-Yong YANG ,  Youngmook OH ,  Bokyoung LEE ,  Seung Mo HA ,  Hyunggoo LEE

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a substrate having a first memory cell and a second memory cell, the first and second memory cells being adjacent to each other in a first direction, first to fourth memory fins adjacent to each other in the first direction in the first memory cell, the first to fourth memory fins protruding from the substrate, fifth to eighth memory fins adjacent to each other in the first direction in the second memory cell, the fifth to eighth memory fins protruding from the substrate, and a first shallow device isolation layer between the fourth memory fin and the fifth memory fin, a sidewall of the first shallow device isolation layer having an inflection point.

公开(公告)号：US20220102493A1

公开(公告)日：2022-03-31

申请号：US17324610

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon PARK ,  Jongchul PARK ,  Bokyoung LEE ,  Jeongyun LEE ,  Hyunggoo LEE ,  Yeondo JUNG ,  Haegeon JUNG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch.. The first distance may be about 0.8 times to about 1.2 times the first pitch.