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    ELECTRONIC DEVICE AND METHOD FOR CHARGING BATTERY
    1.
    发明申请
    ELECTRONIC DEVICE AND METHOD FOR CHARGING BATTERY 审中-公开

    公开(公告)号：US20170294793A1

    公开(公告)日：2017-10-12

    申请号：US15483388

    申请日：2017-04-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Geun YOON ,  Chul-Woo PARK ,  Ku-Chul JUNG ,  Hyun-Deok SEO ,  Min-Jeong LEE

    IPC: H02J7/00

    CPC classification number: H02J7/0072 ,  H02J7/0045 ,  H02J7/045 ,  H02J7/047 ,  H02J2007/0062 ,  H02J2007/0095 ,  H02J2007/0096

    Abstract: Provided are a battery charging method and an electronic device. The electronic device includes a connector that includes a first terminal to which a voltage is applied by an external charger and a second terminal for transmitting and receiving data, and a first charging circuit configured to charge a battery of the electronic device by using the voltage applied to the first terminal. The first charging circuit may include a communication circuit configured to transmit information related to the battery through the second terminal, a voltage converter configured to convert a voltage supplied to the battery and a first controller circuit configured to obtain first information regarding a voltage of the battery, control the communication circuit to transmit the first information to a charger connected with the connector, and control the voltage converter to charge the battery using a voltage adjusted based on the first information by the charger, if the adjusted voltage is applied to the first terminal.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权
    半导体存储器件和存储器系统，包括它们

    公开(公告)号：US20150089327A1

    公开(公告)日：2015-03-26

    申请号：US14444856

    申请日：2014-07-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Youn YOUN ,  Chul-Woo PARK ,  Hak-Soo YU

    IPC: G06F11/16

    CPC classification number: G11C29/886 ,  G06F11/1048 ,  G11C29/76

    Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.

    Abstract translation: 半导体存储器件包括存储单元阵列和纠错码（ECC）电路。 存储单元阵列被分成第一存储区和第二存储区。 第一和第二存储器区域中的每一个包括多个页面，每个页面包括连接到字线的多个存储器单元。 ECC电路使用奇偶校验位校正第一存储区域的单位错误。 第一存储器区域通过使用ECC电路校正单位错误来向外部设备提供连续的地址空间，并且第二存储器区域被保留用于修复第一存储器区域的第一故障页面或第二存储器区域中的至少一个 第二存储器区域的页面。

    VOLATILE MEMORY DEVICE AND REFRESH METHOD THEREOF
    3.
    发明申请
    VOLATILE MEMORY DEVICE AND REFRESH METHOD THEREOF 有权
    易失存储器件及其刷新方法

    公开(公告)号：US20140355332A1

    公开(公告)日：2014-12-04

    申请号：US14219374

    申请日：2014-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Youn YOUN ,  Su-A KIM ,  Chul-Woo PARK ,  Young-Soo SOHN

    IPC: G11C11/406

    CPC classification number: G11C11/40615 ,  G11C7/02 ,  G11C7/1063 ,  G11C11/40611 ,  G11C11/40618

    Abstract: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.

    Abstract translation: 提供了一种易失性存储器件的刷新方法。 该方法包括：随着对第一存储器区域的访问次数的增加，检测影响第二存储器区域的多个干扰; 当检测到的干扰次数达到参考值时，将来自易失性存储器件的警报信号输出到易失性存储器件的外部; 以及响应于所述警报信号对所述第二存储区域执行刷新操作。

    METHOD OF ACCESSING SEMICONDUCTOR MEMORY AND SEMICONDUCTOR CIRCUIT
    4.
    发明申请
    METHOD OF ACCESSING SEMICONDUCTOR MEMORY AND SEMICONDUCTOR CIRCUIT 审中-公开
    接触半导体存储器和半导体电路的方法

    公开(公告)号：US20140247677A1

    公开(公告)日：2014-09-04

    申请号：US14081493

    申请日：2013-11-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Uk-Song KANG ,  Jong-Pil SON

    IPC: G11C11/4076 ,  G11C29/48

    CPC classification number: G11C11/4076 ,  G11C29/842

    Abstract: A method of accessing a semiconductor memory is disclosed which includes outputting a row address and an active command to the semiconductor memory; outputting a column address and a read or write command to the semiconductor memory; and outputting a spare access command to the semiconductor memory to access data from a spare memory cell at a timing based on an additive latency of the semiconductor memory. Related devices and systems are also disclosed.

    Abstract translation: 公开了一种访问半导体存储器的方法，其包括向半导体存储器输出行地址和有效命令; 向半导体存储器输出列地址和读或写命令; 以及基于所述半导体存储器的附加延迟的定时，向所述半导体存储器输出备用访问命令以从备用存储单元访问数据。 还公开了相关的装置和系统。

    STACKED MEMORY DEVICE AND METHOD OF FABRICATING SAME
    5.
    发明申请
    STACKED MEMORY DEVICE AND METHOD OF FABRICATING SAME 有权
    堆叠存储器件及其制造方法

    公开(公告)号：US20130237019A1

    公开(公告)日：2013-09-12

    申请号：US13864437

    申请日：2013-04-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chul-Woo PARK ,  Hong-Sun HWANG ,  In-Gyu BAEK ,  Dong-Hyun SOHN

    IPC: H01L21/77

    CPC classification number: H01L21/77 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/24

    Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

    Abstract translation: 叠层半导体存储器件包括具有功能电路，多个存储单元阵列层以及至少一个连接层的半导体衬底。 存储单元阵列层堆叠在半导体衬底之上。 连接层堆叠在半导体衬底之上，独立于存储单元阵列层。 连接层将布置在存储单元阵列层上的存储单元选择线电连接到功能电路。

    ELECTRONIC DEVICE AND METHOD FOR WIRED AND WIRELESS CHARGING IN ELECTRONIC DEVICE
    6.
    发明申请
    ELECTRONIC DEVICE AND METHOD FOR WIRED AND WIRELESS CHARGING IN ELECTRONIC DEVICE 有权

    公开(公告)号：US20220173622A1

    公开(公告)日：2022-06-02

    申请号：US17675432

    申请日：2022-02-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ku-Chul JUNG ,  Chul-Woo PARK ,  Sung-Geun YOON ,  Sang-Hyun RYU

    IPC: H02J50/12 ,  H04B5/00 ,  H02J50/10 ,  H02J7/00 ,  H02J50/80

    Abstract: An apparatus for wired and wireless charging of an electronic device are provided. The electronic device includes a housing, a display on a surface of the housing, a battery mounted in the housing, a circuit electrically connected with the battery, a conductive pattern positioned in the housing, electrically connected with the circuit, and configured to wirelessly transmit power to an external device, a connector on another surface of the housing and electrically connected with the circuit, a memory, and a processor electrically connected with the display, the battery, the circuit, the connector, and/or the memory. The circuit is configured to electrically connect the battery with the conductive pattern to wirelessly transmit power to the external device and electrically connect the battery with the connector to transmit power to the external device by wire, simultaneously or selectively, with wirelessly transmitting power to the external device.

    ELECTRONIC DEVICE FOR MANAGING POWER AND METHOD OF CONTROLLING SAME
    7.
    发明申请
    ELECTRONIC DEVICE FOR MANAGING POWER AND METHOD OF CONTROLLING SAME 审中-公开

    公开(公告)号：US20200159306A1

    公开(公告)日：2020-05-21

    申请号：US16752053

    申请日：2020-01-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yun-Hui HAN ,  Min-Su KIM ,  Chul-Woo PARK ,  Seung-Chul CHOI

    IPC: G06F1/3206 ,  H02J7/00 ,  G06F1/3234 ,  G06F1/3215 ,  G05B15/02 ,  G06F1/3296 ,  G06F1/3203

    Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权
    半导体存储器件和存储器系统，包括它们

    公开(公告)号：US20150309743A1

    公开(公告)日：2015-10-29

    申请号：US14588496

    申请日：2015-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo SOHN ,  Uk-Song KANG ,  KWANG-IL PARK ,  Chul-Woo PARK ,  Hak-Soo YU ,  Jae-Youn YOUN

    IPC: G06F3/06

    CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4085

    Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

    Abstract translation: 半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。 存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。 控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。 控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。 第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。 因此，可以补偿增加的定时参数，并且可以增加并行性。

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