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公开(公告)号：US20200159306A1
公开(公告)日：2020-05-21
申请号：US16752053
申请日：2020-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yun-Hui HAN , Min-Su KIM , Chul-Woo PARK , Seung-Chul CHOI
IPC: G06F1/3206 , H02J7/00 , G06F1/3234 , G06F1/3215 , G05B15/02 , G06F1/3296 , G06F1/3203
Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.
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公开(公告)号：US20220115369A1
公开(公告)日：2022-04-14
申请号：US17559152
申请日：2021-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Kyu RYU , Min-Su KIM , Yong-Geol KIM , Dae-Seong LEE
IPC: H01L27/02 , H01L23/552 , G03F1/36 , H01L27/118 , G06F30/398
Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.
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公开(公告)号：US20170070071A1
公开(公告)日：2017-03-09
申请号：US15261033
申请日：2016-09-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yun-Hui HAN , Min-Su KIM , Chul-Woo PARK , Seung-Chul CHOI
Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.
Abstract translation: 提供电子设备。 电子设备包括电池，电连接到电池的电源管理集成电路（PMIC），调节从电池接收的至少一部分电力，并且输出受控电力，与PMIC电连接的处理器 至少一个功率传感器，其是电连接在电池和PMIC之间并且构成PMIC的一部分的功率传感器，以及电连接到所述至少一个功率传感器的控制电路。 所述控制电路从所述电池获取输入到所述PMIC的电流值和功率值中的至少一个，判定所获取的电流值和功率值中的至少一个是否大于或等于阈值，并且生成第一信号 用于至少部分地基于所述确定来控制所述PMIC和所述处理器中的至少一个。
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公开(公告)号：US20160315616A1
公开(公告)日：2016-10-27
申请号：US15139949
申请日：2016-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ah-Reum KIM , Hyun LEE , Min-Su KIM
IPC: H03K19/0185 , H03K19/00
CPC classification number: H03K19/01855 , H03K3/012 , H03K3/037 , H03K3/356104 , H03K3/356191 , H03K19/0013
Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.
Abstract translation: 提供半导体电路。 半导体电路包括：第一电路，被配置为基于时钟信号的电压电平将第一节点的值传播到第二节点; 第二电路，被配置为基于所述时钟信号的电压电平将所述第二节点的值传播到第三节点; 以及第三电路，被配置为基于所述第二节点的电压电平和所述时钟信号的电压电平来确定所述第三节点的值，其中所述第一电路包括门控到所述第一节点的电压电平的第一晶体管， 第二晶体管，其与第一晶体管串联连接，并与第三晶体管的电压电平相连，第三晶体管与第一和第二晶体管并联连接，并且选通到时钟信号的电压电平，以提供第一晶体管的值 节点到第二个节点。
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公开(公告)号：US20140362889A1
公开(公告)日：2014-12-11
申请号：US14289166
申请日：2014-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ki-Youn JANG , Min-Su KIM , Kun-Tak KIM , Chi-Hyun CHO
IPC: G01K13/00
Abstract: A method and apparatus for determining a control temperature to control a function of an electronic device by using an atmospheric temperature when controlling a temperature of the electronic device, and for controlling the function of the electronic device according to a control step of the determined control temperature are provided. A method of operating an electronic device includes measuring an atmospheric temperature, determining at least one control temperature corresponding to the measured atmospheric temperature, measuring an internal temperature of the electronic device, and controlling a function in accordance with the measured internal temperature of the electronic device and the determined at least one control temperature.
Abstract translation: 一种用于在控制电子设备的温度时，通过使用大气温度来确定控制温度以控制电子设备的功能的方法和设备，并且用于根据所确定的控制温度的控制步骤来控制电子设备的功能 被提供。 一种操作电子设备的方法包括：测量大气温度，确定与测量的大气温度相对应的至少一个控制温度，测量电子设备的内部温度，以及根据所测量的电子设备的内部温度来控制功能 并确定至少一个控制温度。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200243502A1
公开(公告)日：2020-07-30
申请号：US16521845
申请日：2019-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Min-Su KIM
IPC: H01L27/02 , G06F17/50 , H01L27/118
Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, and first through fourth clock gate lines. The first power rail through third power rails are formed above the semiconductor substrate, and extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through fourth clock gate lines are formed above the semiconductor substrate, and extend in the second direction to pass through a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail. The first clock gate line and the second clock gate line are arranged to be adjacent to each other in the first direction, and the third clock gate line and the fourth clock gate line are arranged to be adjacent to each other in the first direction.
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7.发明申请公开(公告)号：US20190214377A1
公开(公告)日：2019-07-11
申请号：US16105165
申请日：2018-08-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Kyu RYU , Min-Su KIM , Yong-Geol KIM , Dae-Seong LEE
IPC: H01L27/02 , G06F17/50 , H01L23/552 , H01L27/118 , G03F1/36
CPC classification number: H01L27/0207 , G03F1/36 , G06F17/5081 , H01L23/552 , H01L27/11807 , H01L2027/11874 , H01L2027/11892
Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.
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公开(公告)号：US20190074825A1
公开(公告)日：2019-03-07
申请号：US15906693
申请日：2018-02-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Chul HWANG , Jong-Kyu RYU , Min-Su KIM
Abstract: A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.
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公开(公告)号：US20140368246A1
公开(公告)日：2014-12-18
申请号：US14295802
申请日：2014-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chung-Hee KIM , Min-Su KIM , Ji-Kyum KIM , Emil KAGRAMANYAN , Dae-Seong LEE , Gun-Ok JUNG , Uk-Rae CHO
IPC: H03K3/037
CPC classification number: H03K3/0372 , H03K3/0375
Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.
Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。
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10.发明申请公开(公告)号：US20190393205A1
公开(公告)日：2019-12-26
申请号：US16250000
申请日：2019-01-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Seong LEE , Ah-Reum KIM , Min-Su KIM , Jong-Kyu RYU
IPC: H01L27/02 , G06F17/50 , H01L27/092 , H01L23/50
Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.
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