公开(公告)号：US20190393205A1

公开(公告)日：2019-12-26

申请号：US16250000

申请日：2019-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Seong LEE ,  Ah-Reum KIM ,  Min-Su KIM ,  Jong-Kyu RYU

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L23/50

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

公开(公告)号：US20220115369A1

公开(公告)日：2022-04-14

申请号：US17559152

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Kyu RYU ,  Min-Su KIM ,  Yong-Geol KIM ,  Dae-Seong LEE

IPC: H01L27/02 ,  H01L23/552 ,  G03F1/36 ,  H01L27/118 ,  G06F30/398

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

公开(公告)号：US20190214377A1

公开(公告)日：2019-07-11

申请号：US16105165

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Kyu RYU ,  Min-Su KIM ,  Yong-Geol KIM ,  Dae-Seong LEE

IPC: H01L27/02 ,  G06F17/50 ,  H01L23/552 ,  H01L27/118 ,  G03F1/36

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F17/5081 ,  H01L23/552 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2027/11892

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

公开(公告)号：US20190074825A1

公开(公告)日：2019-03-07

申请号：US15906693

申请日：2018-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Chul HWANG ,  Jong-Kyu RYU ,  Min-Su KIM

IPC: H03K5/135 ,  H03K3/356 ,  H03K3/037

Abstract: A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.