公开(公告)号：US20160012880A1

公开(公告)日：2016-01-14

申请号：US14858140

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yun KIM ,  Jong-Pil SON ,  Su-A KIM ,  Chul-Woo PARK ,  Hong-Sun HWANG

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/408 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract translation: 操作易失性存储器件的方法包括存储弱单元行的地址信息。 根据一些示例，在写入弱单元行之后，在预定时间内对弱单元行执行刷新操作。 根据一些示例，可以以对正常单元行的写恢复时间更长的写恢复时间来执行对弱单元行的写入操作。

公开(公告)号：US20240096401A1

公开(公告)日：2024-03-21

申请号：US18199114

申请日：2023-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Young KIM ,  Sang-Yun KIM ,  Younghun SEO

IPC: G11C11/4091 ,  G11C11/408 ,  H10B12/00

CPC classification number: G11C11/4091 ,  G11C11/4085 ,  H10B12/50

Abstract: A semiconductor memory device is provided which is capable of adaptively controlling bias and a method of operating the same. The semiconductor memory device includes: a memory cell area including a plurality of first transistors to which a first bias voltage is applied; and a peripheral circuit area which overlaps the memory cell area in a first direction and includes a plurality of second transistors to which a second bias voltage controlled differently from the first bias voltage is applied.

公开(公告)号：US20180316225A1

公开(公告)日：2018-11-01

申请号：US15965274

申请日：2018-04-27

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Sung-Ku YEO ,  Sang-Yun KIM ,  Jae-Seok PARK ,  Young-Ho RYU ,  Kang-Yoon LEE ,  Hamed ABBASIZADEH ,  Sang-Wook KWON ,  Thi Kim Nga TRUONG ,  Dong-In KIM ,  Sung-Bum PARK ,  Dong-Soo LEE

IPC: H02J50/12 ,  H02J7/00 ,  H02J7/02 ,  H02J50/70

Abstract: An electronic device is provided. The electronic device includes a receiving circuit configured to wirelessly receive power and output AC power, a rectifying circuit configured to rectify the AC power from the receiving circuit, wherein the rectifying circuit may include a first P-MOSFET configured to transfer a positive amplitude of power to an output terminal of the rectifying circuit while the AC power has the positive amplitude and to prevent transferring a negative amplitude of power to the output terminal of the rectifying circuit while the AC power has the negative amplitude, and a forward loss compensating circuit connected with the first P-MOSFET configured to reduce a threshold voltage of the first P-MOSFET while the AC power has the positive amplitude.

公开(公告)号：US20140241093A1

公开(公告)日：2014-08-28

申请号：US14077187

申请日：2013-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Jin LEE ,  Dae-Hyun KIM ,  Sang-Yun KIM ,  Jae-Sung KIM ,  Young-Soo SOHN

IPC: G11C7/00

CPC classification number: G11C11/40611 ,  G11C11/40622 ,  G11C29/028 ,  G11C29/50016

Abstract: A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation.

Abstract translation: 刷新地址生成器可以包括查找表，其包括存储与第一数据保留时间相关联的第一组地址的第一部分，以及存储与第二数据保留时间相关联的第二组地址的第二部分，该第二组地址与第一数据保留不同 时间，其中第一部分的地址比第二部分的地址更频繁地访问以刷新对应于地址的存储单元。 系统和方法也可以实现这种刷新地址生成。

公开(公告)号：US20240064973A1

公开(公告)日：2024-02-22

申请号：US18106620

申请日：2023-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juwon LIM ,  Younghun SEO ,  Sang-Yun KIM

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device includes: a memory cell array located in a first layer and including a word line, a cell bit line, and a memory cell located in a region where the word line and the cell bit line are crossed; and a bit line sense amplifier located in a second layer, different from the first layer. The bit line sense amplifier is connected to a bit line that is connected to the cell bit line and to a complementary bit line corresponding to the bit line. The bit line sense amplifier detects data stored in the at least one memory cell. Each of the at least one cell bit line is segmented into two or more portions, and the two or more portions are respectively connected to the bit line and the complementary bit line connected to the bit line sense amplifier.