知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

95 records (took 0.027 seconds)

    Race-track memory with improved domain wall motion control
    2.
    发明授权
    Race-track memory with improved domain wall motion control 有权

    公开(公告)号：US11348627B2

    公开(公告)日：2022-05-31

    申请号：US17127732

    申请日：2020-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dmytro Apalkov ,  Sungchul Lee ,  Roman Chepulskyy

    IPC: G11C11/00 ,  G11C11/16 ,  G11C11/18

    Abstract: A system including a racetrack memory layer is described. The racetrack memory layer includes a plurality of bit locations and a plurality of domain wall traps. The bit locations are interleaved with the domain wall traps. Each of the bit locations has a first domain wall speed. Each of the domain wall traps has a second domain wall speed. The first domain wall speed is greater than the second domain wall speed. The first domain wall speed and the second domain wall speed are due to at least one of a Dzyaloshinskii-Moriya interaction variation in the racetrack memory layer, a synthetic antiferromagnetic effect variation in the racetrack memory layer, and a separation distance for the plurality of domain wall traps corresponding to an intrinsic travel distance. The separation distance is less than one hundred nanometers.

    Selectorless 3D stackable memory
    3.
    发明授权
    Selectorless 3D stackable memory 有权

    公开(公告)号：US10585630B2

    公开(公告)日：2020-03-10

    申请号：US15845985

    申请日：2017-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Vladimir Nikitin ,  Dmytro Apalkov

    IPC: H01L21/822 ,  H01L27/22 ,  G06F3/06 ,  H01L27/11578 ,  H01L21/3105 ,  G11C11/16 ,  G11C11/18 ,  H01L43/08

    Abstract: A memory device and method for providing the memory device are described. The memory device includes word lines, a first plurality of bit lines, a second plurality of bit lines and selectorless memory cells. Each selectorless memory cell is coupled with a word line, a first bit line of the first plurality of bit lines and a second bit line of the second plurality of bit lines. The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque. The word line is coupled between the first and second magnetic junctions. The first and second bit lines are coupled with the first and second magnetic junctions, respectively. The selectorless memory cell is selected for a write operation based on voltages in the word line, the first bit line and the second bit line.

    METHOD AND SYSTEM FOR ENGINEERING THE SECONDARY BARRIER LAYER IN DUAL MAGNETIC JUNCTIONS
    4.
    发明申请
    METHOD AND SYSTEM FOR ENGINEERING THE SECONDARY BARRIER LAYER IN DUAL MAGNETIC JUNCTIONS 审中-公开

    公开(公告)号：US20190319182A1

    公开(公告)日：2019-10-17

    申请号：US16453854

    申请日：2019-06-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Zheng Duan ,  Dmytro Apalkov ,  Vladimir Nikitin

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

    Abstract: A magnetic junction, a memory using the magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes first and second reference layers, a main barrier layer, a free layer, an engineered secondary barrier layer and a second reference layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The main barrier layer is between the first reference layer and the free layer. The secondary barrier layer is between the free layer and the second reference layer. The engineered secondary barrier layer has a resistance and a plurality of regions having a reduced resistance less than the resistance. The free and reference layers each has a perpendicular magnetic anisotropy energy and an out-of-plane demagnetization energy less than the perpendicular magnetic anisotropy energy.

    Hybrid-fl with edge-modified coupling
    6.
    发明授权
    Hybrid-fl with edge-modified coupling 有权

    公开(公告)号：US10170690B2

    公开(公告)日：2019-01-01

    申请号：US15080572

    申请日：2016-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dmytro Apalkov ,  Donkoun Lee ,  Mohamad Krounbi

    IPC: H01L29/82 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: A magnetic memory device and a method to make the device is disclosed. The magnetic memory device comprises a free magnetic layer that includes a hard magnetic material layer, a soft magnetic material layer and a coupling layer that is between the hard magnetic material layer and the soft magnetic material layer. The coupling layer comprises a magnetic material that has oxidized edges. In one embodiment, the magnetic material of the coupling layer comprises a Heusler alloy or a silicon-based magnetic material. A predetermined amount of the coupling layer is oxidized to controllably reduce the switching current Jc0 of the free magnetic layer to be about half of the switching current if the coupling layer comprised substantially all magnetic material and no oxide.

    Self-assembled pattern process for fabricating magnetic junctions usable in spin transfer torque applications
    7.
    发明授权
    Self-assembled pattern process for fabricating magnetic junctions usable in spin transfer torque applications 有权

    公开(公告)号：US10170518B2

    公开(公告)日：2019-01-01

    申请号：US15659613

    申请日：2017-07-25

    Applicant: Samsung Electronics Co., LTD.

    Inventor： Vladimir Nikitin ,  Dmytro Apalkov ,  Sebastian Schafer

    IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

    Abstract: Magnetic junctions usable in a magnetic device and a method for providing the magnetic junctions are described. A patterned seed layer is provided. The patterned seed layer includes magnetic seed islands interspersed with an insulating matrix. At least a portion of the magnetoresistive stack is provided after the patterned seed layer. The magnetoresistive stack includes at least one magnetic segregating layer. The magnetic segregating layer(s) include at least one magnetic material and at least one insulator. The method anneals the at least the portion of the magnetoresistive stack such that the at least one magnetic segregating layer segregates. The constituents of the magnetic segregating layer segregate such that portions of magnetic material(s) align with the magnetic seed islands(s) and such that portions of the insulator(s) align with the insulating matrix.

    Method and system for providing magnetic junctions with rare earth-transition metal layers
    10.
    发明授权
    Method and system for providing magnetic junctions with rare earth-transition metal layers 有权

    公开(公告)号：US09792971B2

    公开(公告)日：2017-10-17

    申请号：US14730379

    申请日：2015-06-04

    Applicant: Samsung Electronics Co., LTD.

    Inventor： Matthew J. Carey ,  Dmytro Apalkov ,  Keith Chan

    IPC: H01L29/82 ,  G11C11/16 ,  H01L43/12 ,  H01L43/08

    CPC classification number: G11C11/161 ,  G11C11/1675 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic junction usable in magnetic devices is described. The magnetic junction includes a reference layer, a free layer, a nonmagnetic spacer layer between the reference and free layers, and a rare earth-transition metal (RE-TM) layer in the reference and/or free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. If the RE-TM layer is in the free layer then the RE-TM layer is between hard and soft magnetic layers in the free layer. In this aspect, the RE-TM layer has a standby magnetic moment greater than a write magnetic moment. If the RE-TM layer is in the reference layer, then the magnetic junction includes a second RE-TM layer. In this aspect, a first saturation magnetization quantity of the RE-TM layer matches a second saturation magnetization quantity of the second RE-TM layer over an operating temperature range.

Patent Agency Ranking