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公开(公告)号：US20220336669A1
公开(公告)日：2022-10-20
申请号：US17646973
申请日：2022-01-04
发明人： SEOK HWAN BANG , Hyun Seong Kang , Jong-in Kim , Joon Geol Kim , Seung Sok Son , Woo Geun Lee , Young Jae Jeon
IPC分类号： H01L29/786 , H01L29/66
摘要： A display device according to an embodiment includes: a substrate; a first conductive layer positioned on the substrate; a semiconductor layer positioned on the first conductive layer; a second conductive layer positioned on the semiconductor layer; an oxygen supply layer positioned under the second conductive layer, in contact with the second conductive layer, and having the same planar shape as the second conductive layer; and a light-emitting element connected to the second conductive layer, wherein the oxygen supply layer includes a metal oxide that includes one or more of indium, zinc, tin, or gallium, or alloys thereof.
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公开(公告)号：US09281322B2
公开(公告)日：2016-03-08
申请号：US14659120
申请日：2015-03-16
发明人： Seung-Ho Jung , Young Joo Choi , Joon Geol Kim , Kang Moon Jo , Sho Yeon Kim , Byung Hwan Chu , Woo Geun Lee , Woo-Seok Jeon
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1225 , H01L27/1248 , H01L27/1259 , H01L27/1262 , H01L27/1288
摘要： A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.
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公开(公告)号：US20150206818A1
公开(公告)日：2015-07-23
申请号：US14268879
申请日：2014-05-02
发明人： Young Joo Choi , Seung Ho Jung , Joon Geol Kim , Kang Moon Jo
IPC分类号： H01L23/31 , H01B1/02 , G02F1/1333 , G02F1/1335 , G02F1/1368 , G02F1/1362
CPC分类号： H01B1/026 , G02F1/133345 , G02F1/134363 , G02F1/13439 , G02F1/13458 , G02F2001/134318 , G02F2001/13629 , G02F2001/136295 , H01L2924/0002 , H01L2924/00
摘要： A liquid crystal display and a method of fabricating a liquid crystal display (LCD), the LCD including a substrate; gate wiring including a gate pad, a gate electrode, and a gate line, which are formed on the substrate; a gate insulating layer disposed on the gate wiring; an electrode pattern including a connecting electrode, which is disposed on the gate insulating layer and is electrically connected to the gate pad, a source electrode and a drain electrode, which partially overlap the gate electrode; a pixel electrode, which is electrically connected to the drain electrode; a data line, which intersects the gate line; a semiconductor layer disposed on the gate electrode; first auxiliary wiring overlapping the data line and spaced from the semiconductor layer; and second auxiliary wiring overlapping the gate line.
摘要翻译： 液晶显示器和制造液晶显示器（LCD）的方法，所述LCD包括基板; 栅极布线，包括形成在基板上的栅极焊盘，栅电极和栅极线; 设置在栅极布线上的栅极绝缘层; 电极图案，其包括设置在所述栅极绝缘层上并与所述栅极焊盘电连接的连接电极，所述栅电极部分地重叠的源电极和漏电极; 与漏电极电连接的像素电极; 与栅极线相交的数据线; 设置在所述栅电极上的半导体层; 第一辅助布线与数据线重叠并与半导体层间隔开; 并且第二辅助配线与栅极线重叠。
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公开(公告)号：US10553659B2
公开(公告)日：2020-02-04
申请号：US15017742
申请日：2016-02-08
发明人： Joon Geol Kim , Si Joon Kim , Hee Seon Kim
IPC分类号： H01L27/32
摘要： An array test apparatus includes a signal transmission unit which transmits a data signal to each of a plurality of data lines of a low-temperature polysilicon (“LTPS”) substrate, a signal measurement unit which measures the data signal of each of the data lines of the LTPS substrate, a timer which generates a horizontal period for setting a section in which the data signal is transmitted from the signal transmission unit to each of the data lines and a section in which the data signal output from each of the data lines is measured by the signal measurement unit, and a determination unit which determines whether each of the data lines of the LTPS substrate is normal based on the data signal measured by the signal measurement unit.
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公开(公告)号：US09496063B2
公开(公告)日：2016-11-15
申请号：US14268879
申请日：2014-05-02
发明人： Young Joo Choi , Seung Ho Jung , Joon Geol Kim , Kang Moon Jo
IPC分类号： H01L29/739 , H01B1/02 , G02F1/1333 , G02F1/1343 , G02F1/1345 , G02F1/1362
CPC分类号： H01B1/026 , G02F1/133345 , G02F1/134363 , G02F1/13439 , G02F1/13458 , G02F2001/134318 , G02F2001/13629 , G02F2001/136295 , H01L2924/0002 , H01L2924/00
摘要： A liquid crystal display and a method of fabricating a liquid crystal display (LCD), the LCD including a substrate; gate wiring including a gate pad, a gate electrode, and a gate line, which are formed on the substrate; a gate insulating layer disposed on the gate wiring; an electrode pattern including a connecting electrode, which is disposed on the gate insulating layer and is electrically connected to the gate pad, a source electrode and a drain electrode, which partially overlap the gate electrode; a pixel electrode, which is electrically connected to the drain electrode; a data line, which intersects the gate line; a semiconductor layer disposed on the gate electrode; first auxiliary wiring overlapping the data line and spaced from the semiconductor layer; and second auxiliary wiring overlapping the gate line.
摘要翻译： 液晶显示器和制造液晶显示器（LCD）的方法，所述LCD包括基板; 栅极布线，包括形成在基板上的栅极焊盘，栅电极和栅极线; 设置在栅极布线上的栅极绝缘层; 电极图案，其包括设置在所述栅极绝缘层上并与所述栅极焊盘电连接的连接电极，所述栅电极部分地重叠的源电极和漏电极; 与漏电极电连接的像素电极; 与栅极线相交的数据线; 设置在所述栅电极上的半导体层; 第一辅助布线与数据线重叠并与半导体层间隔开; 并且第二辅助配线与栅极线重叠。
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6.发明授权Thin film transistor array panel having double-layered oxide semiconductor structure and method for manufacturing the same 有权具有双层氧化物半导体结构的薄膜晶体管阵列面板及其制造方法公开(公告)号：US09209313B2
公开(公告)日：2015-12-08
申请号：US14291535
申请日：2014-05-30
发明人： Young Joo Choi , Joon Geol Kim , Seung-Ho Jung , Kang Moon Jo
IPC分类号： G02F1/1343 , H01L29/786 , H01L29/66 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/124 , H01L27/1259 , H01L29/45 , H01L29/66742 , H01L29/66969 , H01L29/78618
摘要： A thin film transistor array panel includes: a gate line including a gate electrode; a first gate insulating layer on the gate line; a semiconductor layer on the first gate insulating layer and overlapping the gate electrode; a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and an opening in the second gate insulating layer and through which the semiconductor layer is exposed; drain and source electrodes on the second gate insulating and semiconductor layers and facing each other; a first field generating electrode; and a second field generating electrode connected to the drain electrode. The semiconductor layer includes an oxide semiconductor layer, and first and second auxiliary layers on the oxide semiconductor layer and separated from each other. An edge of the drain and source electrodes is disposed inside an edge of the first and second auxiliary layers, respectively.
摘要翻译： 薄膜晶体管阵列面板包括：栅极线，包括栅电极; 栅极线上的第一栅极绝缘层; 在所述第一栅极绝缘层上的半导体层，并且与所述栅电极重叠; 在所述半导体层和所述第一栅极绝缘层上的第二栅极绝缘层和所述第二栅极绝缘层中的所述半导体层暴露的开口; 第二栅绝缘层和半导体层上的漏极和源极彼此面对; 第一场产生电极; 以及连接到漏电极的第二场产生电极。 半导体层包括氧化物半导体层，以及氧化物半导体层上的第一和第二辅助层，并且彼此分离。 漏极和源电极的边缘分别设置在第一和第二辅助层的边缘的内侧。
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公开(公告)号：US11107866B2
公开(公告)日：2021-08-31
申请号：US16725280
申请日：2019-12-23
发明人： Joon Geol Kim , Si Joon Kim , Hee Seon Kim
IPC分类号： G01R31/00 , H01L27/32 , G09G3/3233 , G09G3/00
摘要： An array test apparatus includes a signal transmission unit which transmits a data signal to each of a plurality of data lines of a low-temperature polysilicon (“LTPS”) substrate, a signal measurement unit which measures the data signal of each of the data lines of the LTPS substrate, a timer which generates a horizontal period for setting a section in which the data signal is transmitted from the signal transmission unit to each of the data lines and a section in which the data signal output from each of the data lines is measured by the signal measurement unit, and a determination unit which determines whether each of the data lines of the LTPS substrate is normal based on the data signal measured by the signal measurement unit.
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公开(公告)号：US20160300950A1
公开(公告)日：2016-10-13
申请号：US14887483
申请日：2015-10-20
发明人： Hyeon Jun LEE , Ki Won Kim , Yoo Ho Kim , Joon Geol Kim , Doo Hyoung Lee
IPC分类号： H01L29/786 , H01L29/423 , H01L29/45 , H01L21/4763 , H01L29/22 , H01L29/66 , H01L21/44 , H01L27/12 , H01L29/24
CPC分类号： H01L29/7869 , H01L21/44 , H01L27/1225 , H01L27/124 , H01L27/1244 , H01L27/1259 , H01L29/22 , H01L29/24 , H01L29/42384 , H01L29/45 , H01L29/66969 , H01L29/78618
摘要： A thin film transistor array panel includes a gate line disposed on a substrate, the gate line including a gate electrode, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the substrate, the semiconductor layer including an oxide semiconductor, a data line disposed on the substrate and crossing the gate line, a data line layer including a source electrode connected to the data line and a drain electrode facing the source electrode, and a passivation layer covering the source electrode and the drain electrode. The data line layer includes copper or a copper alloy, and the semiconductor layer includes a copper doped oxide semiconductor. A content of copper doped on the oxide semiconductor is 0.2% to 0.82%.
摘要翻译： 薄膜晶体管阵列面板包括设置在基板上的栅极线，栅极线包括栅极电极，设置在栅电极上的栅极绝缘层，设置在基板上的半导体层，包括氧化物半导体的半导体层， 数据线，设置在基板上并与栅极线交叉;数据线层，包括连接到数据线的源电极和面对源电极的漏极，以及覆盖源电极和漏电极的钝化层。 数据线层包括铜或铜合金，并且半导体层包括掺铜氧化物半导体。 氧化物半导体上掺杂的铜的含量为0.2〜0.82％。
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公开(公告)号：US09012994B2
公开(公告)日：2015-04-21
申请号：US14012580
申请日：2013-08-28
发明人： Seung-Ho Jung , Young Joo Choi , Joon Geol Kim , Kang Moon Jo , Sho Yeon Kim , Byung Hwan Chu , Woo Geun Lee , Woo-Seok Jeon
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1225 , H01L27/1248 , H01L27/1259 , H01L27/1262 , H01L27/1288
摘要： A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.
摘要翻译： 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。
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