公开(公告)号：US09287297B2

公开(公告)日：2016-03-15

申请号：US14486620

申请日：2014-09-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sho Yeon Kim ,  Hyun Kim ,  Eun Hye Park ,  Byung Hwan Chu ,  Seung-Ha Choi

IPC: H01L31/036 ,  H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate electrode of a display area, a gate insulating layer disposed on the substrate and having a first contact hole exposing the first connection member, a semiconductor layer disposed on a region of the gate insulating layer, a data line disposed on the gate insulating layer and the semiconductor layer and including a drain electrode, a source electrode, and a second connection member connected to the first connection member through the first contact hole, a passivation layer disposed on the data line, the source electrode, the drain electrode, and the second connection member, and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode. A horizontal width of the first contact hole ranges from 1 to 2 μm.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，其设置在基板上，并且包括栅极驱动器区域的第一连接构件和显示区域的栅极电极，栅极绝缘层，设置在所述基板上，并且具有暴露于所述第一接触孔 所述第一连接构件，设置在所述栅极绝缘层的区域上的半导体层，设置在所述栅极绝缘层和所述半导体层上的数据线，并且包括漏电极，源电极和连接到所述第一连接构件的第二连接构件 连接构件，通过第一接触孔，设置在数据线上的钝化层，源电极，漏电极和第二连接构件，以及设置在钝化层上并电连接到漏电极的像素电极。 第一接触孔的水平宽度为1〜2μm。

公开(公告)号：US09281322B2

公开(公告)日：2016-03-08

申请号：US14659120

申请日：2015-03-16

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho Jung ,  Young Joo Choi ,  Joon Geol Kim ,  Kang Moon Jo ,  Sho Yeon Kim ,  Byung Hwan Chu ,  Woo Geun Lee ,  Woo-Seok Jeon

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

公开(公告)号：US11552108B2

公开(公告)日：2023-01-10

申请号：US17122859

申请日：2020-12-15

Applicant: Samsung Display Co., Ltd.

Inventor： Byung Hwan Chu ,  Sho Yeon Kim ,  Wan-Soon Im ,  Yong Tae Cho

IPC: H01L27/12 ,  G09G3/20 ,  H01L29/423 ,  H01L29/417

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

公开(公告)号：US09455278B2

公开(公告)日：2016-09-27

申请号：US15053807

申请日：2016-02-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sho Yeon Kim ,  Hyun Kim ,  Eun Hye Park ,  Byung Hwan Chu ,  Seung-Ha Choi

IPC: H01L31/036 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate electrode of a display area, a gate insulating layer disposed on the substrate and having a first contact hole exposing the first connection member, a semiconductor layer disposed on a region of the gate insulating layer, a data line disposed on the gate insulating layer and the semiconductor layer and including a drain electrode, a source electrode, and a second connection member connected to the first connection member through the first contact hole, a passivation layer disposed on the data line, the source electrode, the drain electrode, and the second connection member, and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode. A horizontal width of the first contact hole ranges from 1 to 2 μm.

公开(公告)号：US20210104553A1

公开(公告)日：2021-04-08

申请号：US17122859

申请日：2020-12-15

Applicant: Samsung Display Co., Ltd.

Inventor： Byung Hwan Chu ,  Sho Yeon Kim ,  Wan-Soon Im ,  Yong Tae Cho

IPC: H01L27/12 ,  G09G3/20 ,  H01L29/423

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

公开(公告)号：US10515985B2

公开(公告)日：2019-12-24

申请号：US16059088

申请日：2018-08-09

Applicant: Samsung Display Co., Ltd.

Inventor： Byung Hwan Chu ,  Sho Yeon Kim ,  Wan-Soon Im ,  Yong Tae Cho

IPC: H01L27/12 ,  G09G3/20 ,  H01L29/423 ,  H01L29/417

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

公开(公告)号：US09012994B2

公开(公告)日：2015-04-21

申请号：US14012580

申请日：2013-08-28

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho Jung ,  Young Joo Choi ,  Joon Geol Kim ,  Kang Moon Jo ,  Sho Yeon Kim ,  Byung Hwan Chu ,  Woo Geun Lee ,  Woo-Seok Jeon

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。