公开(公告)号：US20160293258A1

公开(公告)日：2016-10-06

申请号：US15067751

申请日：2016-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-SANG LEE

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: A nonvolatile memory device includes memory cells stacked in a direction perpendicular to a substrate and further includes a first memory cell string connected between a selected bit line and a selected string selection line, a second memory cell string connected between the selected bit line and an unselected string selection line, and a third memory cell string connected to an unselected bit line. During a bit line setup section of a program operation, a ground voltage is provided to the selected bit line and a power supply voltage provided to the unselected string selection line is changed to the ground voltage.

Abstract translation: 非易失性存储器件包括沿垂直于衬底的方向堆叠的存储器单元，并且还包括连接在所选位线和所选择的串选择线之间的第一存储单元串，连接在所选位线和未选择位线之间的第二存储单元串 串选择线，以及连接到未选位线的第三存储单元串。 在编程操作的位线设置部分期间，将地电压提供给所选择的位线，并且提供给未选择的串选择线的电源电压被改变为接地电压。

公开(公告)号：US20230142279A1

公开(公告)日：2023-05-11

申请号：US17953003

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNHYANG PARK ,  JOONSUC JANG ,  SE HWAN PARK ,  JI-SANG LEE

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3404

Abstract: A flash memory device includes a memory cell array connected with word lines and control logic that performs threshold voltage compensation on the word lines through a data recover read operation. When a word line on which programming is performed after a selected word line is a dummy word line, the control logic performs the threshold voltage compensation on the selected word line based on a result of a data recover read operation of a word line on which programming is performed before the selected word line. When a next word line on which programming is performed after a selected word line is a dummy word line, the control logic performs threshold voltage compensation on the selected word line based on a result of performing the data recover read operation on a previous word line on which programming is performed before the selected word line.

公开(公告)号：US20220101930A1

公开(公告)日：2022-03-31

申请号：US17359688

申请日：2021-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANGHO CHOI ,  JIN-YOUNG KIM ,  SE HWAN PARK ,  IL HAN PARK ,  JI-SANG LEE ,  JOONSUC JANG

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

公开(公告)号：US20180190363A1

公开(公告)日：2018-07-05

申请号：US15639459

申请日：2017-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-SANG LEE

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3431 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3418 ,  G11C16/3459

Abstract: A nonvolatile memory device may include a memory cell array and a control logic. The memory cell array has a plurality of memory cells connected to a plurality of word lines. The control logic controls, in a transition process from a verification step to a bit line setup step for a program operation of the plurality of memory cells, an application of a recovery voltage to a word line among the plurality of word lines. The recovery voltage applied to the word line is different from a recovery voltage applied to other word lines.

公开(公告)号：US20140010017A1

公开(公告)日：2014-01-09

申请号：US13915688

申请日：2013-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-SANG LEE ,  MOOSUNG KIM

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3454 ,  G11C16/3495 ,  G11C2211/5641

Abstract: A method of reading a nonvolatile memory device comprises applying a read voltage to a memory cell array to read selected memory cells, counting a number of the selected memory cells that have a threshold voltage higher or lower than the read voltage, and comparing the counted number with a reference value to determine a number of bits stored in the selected memory cells.

Abstract translation: 读取非易失性存储器件的方法包括将读取电压施加到存储器单元阵列以读取所选择的存储器单元，对具有高于或低于读取电压的阈值电压的所选存储单元的数量进行计数，以及将所计数的数目 具有用于确定存储在所选择的存储器单元中的位数的参考值。

公开(公告)号：US20230125101A1

公开(公告)日：2023-04-27

申请号：US18088046

申请日：2022-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANGHO CHOI ,  JIN-YOUNG KIM ,  SE HWAN PARK ,  IL HAN PARK ,  JI-SANG LEE ,  JOONSUC JANG

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

公开(公告)号：US20180068728A1

公开(公告)日：2018-03-08

申请号：US15806543

申请日：2017-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-SANG LEE ,  DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

公开(公告)号：US20160027513A1

公开(公告)日：2016-01-28

申请号：US14695866

申请日：2015-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-SANG LEE

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: A nonvolatile memory device includes memory cells stacked in a direction perpendicular to a substrate and further includes a first memory cell string connected between a selected bit line and a selected string selection line, a second memory cell string connected between the selected bit line and an unselected string selection line, and a third memory cell string connected to an unselected bit line. During a bit line setup section of a program operation, a ground voltage is provided to the selected bit line and a power supply voltage provided to the unselected string selection line is changed to the ground voltage.

公开(公告)号：US20150155046A1

公开(公告)日：2015-06-04

申请号：US14554128

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-SANG LEE ,  KI-HWAN CHOI ,  OH-SUK KWON

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/3459

Abstract: A nonvolatile memory device, including a first latch unit and a nonvolatile memory cell, and a method of writing data in a nonvolatile memory device are provided. The method includes receiving a first writing command or a second writing command from outside of the nonvolatile memory device, and writing first data stored in the first latch unit in the nonvolatile memory cell in response to the first or second writing command. The first data is retained in the first latch unit until the writing of the first data stored in the first latch unit in the nonvolatile memory cell is completed.

Abstract translation: 提供了包括第一锁存单元和非易失性存储单元的非易失性存储器件以及将数据写入非易失性存储器件的方法。 该方法包括从非易失性存储装置的外部接收第一写入命令或第二写入命令，以及响应于第一或第二写入命令将存储在第一锁存单元中的第一数据写入非易失性存储单元。 第一数据被保留在第一锁存单元中，直到存储在非易失性存储单元中的第一锁存单元中的第一数据的写入完成。