公开(公告)号：US09768070B1

公开(公告)日：2017-09-19

申请号：US15160007

申请日：2016-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Suk Lee ,  Dong-Kwon Kim

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/50 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/823437 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475

Abstract: Provided is a method for manufacturing a semiconductor device, which can secure a sufficient margin in a process of forming a self-aligned contact. The method includes forming a plurality of gate structures arranged in parallel on a substrate and being spaced apart from each other, each of the plurality of gate structures including a conductive layer and a capping layer formed on the conductive layer, forming a first insulation layer between each of the plurality of gate structures, recessing top portions of the plurality of gate structures, forming a block layer along a top surface of the first insulation layer and the recessed top portions of the plurality of gate structures, forming a hardmask layer on the block layer, forming a hardmask pattern on each of the plurality of gate structures by planarizing a top portion of the block layer and a top portion of the hardmask layer, and forming a second insulation layer along a top surface of the block layer and top surfaces of the hardmask patterns.

公开(公告)号：US09716041B2

公开(公告)日：2017-07-25

申请号：US14751594

申请日：2015-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kwon Kim ,  Kang-Ill Seo

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/417 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for fabricating a semiconductor device includes forming a pre-fin extending in a first direction, the pre-fin including first, second, and third regions, forming first and second gates on the pre-fin to extend in a second direction intersecting the first direction, the first and second gates being spaced apart from each other in the first direction and overlapping with the first and second regions, respectively, forming first and second dummy spacers on the first and second regions, respectively to form a first trench in the third region that exposes the third region, forming a second trench by etching the exposed third region using the first and second dummy spacers as masks to separate the pre-fin into first and second active fins corresponding to the first and second regions, respectively, forming a dummy gate by filling the first and second trenches and removing the first and second dummy spacers.

公开(公告)号：US09627514B1

公开(公告)日：2017-04-18

申请号：US15188619

申请日：2016-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kwon Kim ,  Ji-Hoon Cha

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/66795 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device is provided as follows. Epitaxial layers is formed on an active fin structure of a substrate. First metal gate electrodes are formed on the active fin structure. Each first metal gate electrode and each epitaxial layer are alternately disposed in a first direction on the active fin structure. ILD patterns are formed on the epitaxial layers, extending in a second direction crossing the first direction. Sacrificial spacer patterns are formed on the first metal gate electrodes. Each of the plurality of sacrificial spacer patterns covers a corresponding first metal gate electrode of the first metal gate electrodes. Self-aligned contact holes and sacrificial spacers are formed by removing the ILD patterns. Each self-aligned contact hole exposes a corresponding epitaxial layer disposed under each ILD pattern. Source/drain electrodes are formed in the self-aligned contact holes. The sacrificial spacers are replaced with air spacers.

公开(公告)号：US09972683B2

公开(公告)日：2018-05-15

申请号：US15145040

申请日：2016-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kwon Kim ,  Ji-Hoon Cha

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/16 ,  H01L49/02

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165

Abstract: A method of fabricating a semiconductor device is provided as follows. A strain relaxed buffer (SRB) layer is formed on a substrate. The SRB layer is formed of a first silicon germanium alloy (SiGe) layer which has a first atomic percent of germanium (Ge) atoms. A heterogeneous channel layer is formed on the SRB layer. The heterogeneous channel layer includes a silicon layer on a first region of the SRB layer and a second SiGe layer on a second region of the SRB layer. The second SiGe layer includes a second atomic percent of germanium greater than the first atomic percent of germanium atoms. The silicon layer is in contact with the second SiGe layer.

公开(公告)号：US09755034B2

公开(公告)日：2017-09-05

申请号：US14923982

申请日：2015-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kwon Kim ,  Kang-Ill Seo

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/785

Abstract: A semiconductor device is provided as follows. A first nanowire is disposed on a substrate. The first nanowire is extended in a first direction and spaced apart from the substrate. A gate electrode surrounds a periphery of the first nanowire. The gate electrode is extended in a second direction intersecting the first direction. A gate spacer is formed on a sidewall of the gate electrode. The gate spacer includes an inner sidewall and an outer sidewall facing each other. The inner sidewall of the gate spacer faces the sidewall of the gate electrode. An end portion of the first nanowire is protruded from the outer sidewall of the gate spacer. A source/drain epitaxial layer is disposed on at least one side of the gate electrode. The source/drain is connected to the protruded end portion of the first nanowire.

公开(公告)号：US09318478B1

公开(公告)日：2016-04-19

申请号：US14610046

申请日：2015-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok-Han Bae ,  Dong-Kwon Kim ,  Jong-Hyuk Kim ,  Yoon-Moon Park

IPC: H01L27/088 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/0886

Abstract: A semiconductor device includes a first dummy gate having a first width, a second dummy gate adjacent to the first dummy gate in a lengthwise direction and having a second width, and a first bridge connecting the first dummy gate and the second dummy gate to each other. The first width and the second width are smaller than a minimum processing line width.

Abstract translation: 半导体器件包括具有第一宽度的第一伪栅极和与第一虚设栅极相邻的具有第二宽度的第二伪栅极，以及将第一伪栅极和第二伪栅极彼此连接的第一桥接器 。 第一宽度和第二宽度小于最小处理线宽度。

公开(公告)号：US09831119B2

公开(公告)日：2017-11-28

申请号：US15189660

申请日：2016-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kwon Kim

IPC: H01L21/76 ,  H01L21/70 ,  H01L21/768 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/7682 ,  H01L21/76264 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L2221/1063

Abstract: A method of fabricating a semiconductor device is provided as follows. An epitaxial layer is formed on an active fin structure. Metal gate electrodes are formed on the active fin structure. Gate electrode caps are formed on upper surfaces of the metal gate electrodes. Metal gate spacers are formed on sidewalls of the metal gate electrodes. A source/drain electrode is formed on the epitaxial layer. An air spacer region is formed by removing the metal gate electrode caps and the metal gate spacers. An air spacer is formed within the air spacer region.

公开(公告)号：US09818825B2

公开(公告)日：2017-11-14

申请号：US15145252

申请日：2016-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kwon Kim ,  Yong-Woo Lee

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/16 ,  H01L27/11

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165

Abstract: A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.