公开(公告)号：US20230361032A1

公开(公告)日：2023-11-09

申请号：US17969440

申请日：2022-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk HONG ,  Jaemyung Choi ,  Jaejik Baek ,  Janggeun Lee ,  Myunghoon Jung ,  Taesun Kim ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76885 ,  H01L21/76865 ,  H01L23/5226

Abstract: A semiconductor device includes a dielectric layer, a plurality of vias formed in the dielectric layer, an adhesion layer deposited on a top surface of the dielectric layer, and a plurality of metal lines. A first metal line of the plurality of metal lines includes a first recess formed at a bottom surface of the first metal line such that a first section of the first metal line directly contacts the first via and a second section of the first metal line defined by the first recess does not directly contact the first via or the dielectric layer in which the first via is formed.

公开(公告)号：US20230343839A1

公开(公告)日：2023-10-26

申请号：US17885237

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Sung KIM ,  Jaejik BAEK ,  Wonhyuk HONG ,  Myunghoon JUNG ,  Jongjin LEE ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L29/401 ,  H01L29/0673

Abstract: Provided is a semiconductor device that includes: at least one transistor, a front side structure, and a back side structure, the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor and connecting the front side structure to the back side structure, wherein the front via is formed in a via hole formed of a lower via hole and an upper via hole vertically connected to each other, and wherein the via hole has a bent structure at a side surface thereof where the lower via hole is connected to the upper via hole.

公开(公告)号：US20220157736A1

公开(公告)日：2022-05-19

申请号：US17590238

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Rakhwan KIM ,  Eun-Ji JUNG

IPC: H01L23/532 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20240290866A1

公开(公告)日：2024-08-29

申请号：US18540280

申请日：2023-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Taesun KIM ,  Myunghoon JUNG ,  Kang-ill SEO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A system and a method are disclosed for forming a bottle-neck shaped backside contact structure in a semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side partially within the first source/drain structure, a second side contacting a backside power rail, and a liner extending from the first side to the backside power rail. The liner includes a first region comprised of either a Ta silicide liner or a Ti silicide liner, a second region comprised of a Ti/TiN liner and a third region comprised of either a Ta silicide liner or a Ti silicide liner. The backside contact structure includes a first portion having a positive slope and a second portion, adjacent to the first portion, having no slope.

公开(公告)号：US20210183786A1

公开(公告)日：2021-06-17

申请号：US16940933

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Rakhwan KIM ,  Eun-Ji JUNG

IPC: H01L23/532 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/768

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20250151362A1

公开(公告)日：2025-05-08

申请号：US18756482

申请日：2024-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk HONG ,  Jongjin Lee ,  Tae Sun Kim ,  Kang-ill Seo

IPC: H01L29/417 ,  H01L21/285 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which includes: a channel structure; a gate structure on the channel structure; a 1st source/drain region on the channel structure; a substrate layer below the gate structure; a 1st etch-stop layer below the substrate layer; a backside spacer on side surfaces of the substrate layer and the 1st etch-stop layer; and a backside contact structure on a bottom surface of the 1st source/drain region and a side surface of the backside spacer.

公开(公告)号：US20250022797A1

公开(公告)日：2025-01-16

申请号：US18378789

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemyung CHOI ,  Janggeun LEE ,  Wonhyuk HONG ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes: a frontside structure including at least one of a front-end-of-line (FEOL) structure, a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a 1st metal line on the frontside structure; and a 2nd metal line on the frontside structure, wherein the 1st metal line has a greater width than the 2nd metal line in a same direction, and the 1st metal line and the 2nd metal line have an equal height.

公开(公告)号：US20240105615A1

公开(公告)日：2024-03-28

申请号：US18110296

申请日：2023-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongjin LEE ,  Wonhyuk HONG ,  Kang-Ill SEO

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is field-effect transistor structure including: a channel structure; a source/drain region and a 2nd source/drain region connected to each other through the channel structure; a 1st contact plug, on a top surface of the 1st source/drain region, connected to a voltage source or 1st circuit element through a back-end-of-line (BEOL) structure; and a 2nd contact plug, on a bottom surface of the 2nd source/drain region, connected to the 1st voltage source, through a backside power rail, or another circuit element, wherein the 1st source/drain region and the 2nd source/drain region have a substantially same height.