公开(公告)号：US20150372143A1

公开(公告)日：2015-12-24

申请号：US14310640

申请日：2014-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Il BAE ,  Kang-Ill SEO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/423

CPC classification number: H01L29/161 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided. A fin type active pattern, extending in a first direction, protrudes from a substrate. A gate electrode is disposed on the fin type active pattern. The gate electrode extends in a second direction crossing the first direction. A recess region is disposed in the fin type active pattern disposed at one side of the gate electrode. The recess region includes an upper region having a first width in the first direction and a lower region having a second width smaller than the first width. A first epitaxial layer is disposed on the upper and lower regions of the recess region. A second epitaxial layer is disposed on the first epitaxial layer to fill the recess region.

Abstract translation: 提供半导体器件。 从第一方向延伸的翅片型有源图案从基板突出。 栅极电极设置在翅片型有源图案上。 栅电极沿与第一方向交叉的第二方向延伸。 在设置在栅电极的一侧的翅片型有源图案中设置有凹部区域。 凹部区域包括在第一方向上具有第一宽度的上部区域和具有小于第一宽度的第二宽度的下部区域。 第一外延层设置在凹陷区域的上部和下部区域上。 第二外延层设置在第一外延层上以填充凹陷区域。

公开(公告)号：US20240105615A1

公开(公告)日：2024-03-28

申请号：US18110296

申请日：2023-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongjin LEE ,  Wonhyuk HONG ,  Kang-Ill SEO

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is field-effect transistor structure including: a channel structure; a source/drain region and a 2nd source/drain region connected to each other through the channel structure; a 1st contact plug, on a top surface of the 1st source/drain region, connected to a voltage source or 1st circuit element through a back-end-of-line (BEOL) structure; and a 2nd contact plug, on a bottom surface of the 2nd source/drain region, connected to the 1st voltage source, through a backside power rail, or another circuit element, wherein the 1st source/drain region and the 2nd source/drain region have a substantially same height.

公开(公告)号：US20240145343A1

公开(公告)日：2024-05-02

申请号：US18133872

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae PARK ,  Jintae KIM ,  Hyoeun PARK ,  Kang-Ill SEO

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/481 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A cell architecture including at least one semiconductor device cell is provided. The cell includes: a 1st active pattern and a 2nd active pattern extended in a 1st direction, the 1st active pattern at least partially overlapping the 2nd active pattern in a 3rd direction intersecting the direction; a plurality of gate structures extended in a 2nd direction across the 1st and 2nd active patterns, the 2nd direction intersecting the 1st direction and the 3rd direction; a plurality of metal lines in at least one metal layer of the cell, the metal lines being extended in the 1st direction, and at least one of the metal lines being connected to at least one of the 1st and 2nd active patterns and the gate structures; and at least one power rail connecting the at least one of the 1st and 2nd active patterns to at least one voltage source, wherein the at least one power rail is disposed to be closer to a virtual horizontal center line of the cell extended in the 1st direction than an upper boundary or a lower boundary of the cell.