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    Insulated gate bipolar transistor
    1.
    发明授权
    Insulated gate bipolar transistor 有权
    绝缘栅双极晶体管

    公开(公告)号：US09318589B2

    公开(公告)日：2016-04-19

    申请号：US13751916

    申请日：2013-01-28

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Jaehoon Park ,  Chang Su Jang ,  In Hyuk Song ,  Kee Ju Um ,  Dong Soo Seo

    IPC: H01L29/739 ,  H01L29/10

    CPC classification number: H01L29/7397 ,  H01L29/1095

    Abstract: There is provided an insulated gate bipolar transistor including: a first semiconductor area of a first conductivity type; a second semiconductor area of a second conductivity type formed on one surface of the first semiconductor area; third semiconductor areas of the first conductivity type continuously formed in a length direction on one surface of the second semiconductor area; a plurality of trenches formed between the third semiconductor areas, extending to an inside of the second semiconductor area, and being continuous in the length direction; a fourth semiconductor area of the second conductivity type formed on one surface of the third semiconductor areas, insulation layers formed inside the trenches; gate electrodes buried inside the insulation layers; and a barrier layer formed in at least one of locations corresponding to the third semiconductor areas inside the second semiconductor area.

    Abstract translation: 提供了一种绝缘栅双极晶体管，包括：第一导电类型的第一半导体区域; 形成在第一半导体区域的一个表面上的第二导电类型的第二半导体区域; 在第二半导体区域的一个表面上沿长度方向连续形成的第一导电类型的第三半导体区域; 多个沟槽，形成在第三半导体区域之间，延伸到第二半导体区域的内部，并且在长度方向上是连续的; 形成在第三半导体区域的一个表面上的第二导电类型的第四半导体区域，形成在沟槽内的绝缘层; 掩埋在绝缘层内的栅电极; 以及形成在与所述第二半导体区域内的所述第三半导体区域对应的位置中的至少一个的阻挡层。

    POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    功率半导体器件及其制造方法

    公开(公告)号：US20140167150A1

    公开(公告)日：2014-06-19

    申请号：US13871082

    申请日：2013-04-26

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Kee Ju UM ,  In Hyuk Song ,  Chang Su Jang ,  Jaehoon Park ,  Dong Soo Seo

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7397 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66348

    Abstract: There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion.

    Abstract translation: 提供了一种功率半导体器件，包括形成在有源区中的触点，从第一区延伸形成第一终端区并与触点交替形成的沟槽栅，形成在有源区的触点和 沟槽栅极，形成在第一端接区域中的第一导电阱延伸部分和第二端接区域的一部分，以及形成在第二端接区域中并接触阱延伸部分的第一导电场限制环。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140167103A1

    公开(公告)日：2014-06-19

    申请号：US14049992

    申请日：2013-10-09

    Applicant: Samsung Electro-Mechanics Co., Ltd.

    Inventor： Jaehoon Park ,  Inhyuk Song ,  Dongsoo Seo ,  Kwangsoo Kim ,  Keeju Um

    IPC: H01L29/739 ,  H01L29/66

    CPC classification number: H01L29/7397 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396

    Abstract: Disclosed herein is a semiconductor device including a semiconductor substrate, a collector layer formed under the semiconductor substrate, a base layer formed on the semiconductor substrate, an emitter layer formed on the base layer, one or more trench barriers vertically penetrating the base layer and the emitter layer, a first gate insulating layer formed on the trench barriers and the emitter layer such that an upper portion of the emitter layer is partially exposed, a gate formed on the first gate insulating layer, a second gate insulating layer formed to cover the gate, and an emitter metal layer formed on an upper portion of the emitter layer exposed by the first gate insulating layer.

    Abstract translation: 本发明公开了一种半导体器件，包括半导体衬底，形成在半导体衬底下面的集电极层，形成在半导体衬底上的基极层，形成于基底层上的发射极层，垂直穿透基底层的一个或多个沟槽屏障和 发射极层，形成在所述沟槽屏障和所述发射极层上的第一栅极绝缘层，使得所述发射极层的上部被部分暴露，形成在所述第一栅极绝缘层上的栅极，形成为覆盖所述栅极的第二栅极绝缘层 以及形成在由第一栅极绝缘层暴露的发射极层的上部的发射极金属层。

    Power semiconductor device and method of fabricating the same
    8.
    发明授权
    Power semiconductor device and method of fabricating the same 有权
    功率半导体器件及其制造方法

    公开(公告)号：US08981423B2

    公开(公告)日：2015-03-17

    申请号：US13937589

    申请日：2013-07-09

    Applicant: Samsung Electro-Mechanics Co., Ltd.

    Inventor： Dong Soo Seo ,  Jaehoon Park ,  Kee Ju Um ,  Chang Su Jang ,  In Hyuk Song

    IPC: H01L29/66 ,  H01L29/739

    CPC classification number: H01L29/7395 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/7397

    Abstract: There is provided a power semiconductor device, including a plurality of trench gates formed to be spaced apart from each other by a predetermined distance, a current increasing part formed between the trench gates and including a first conductivity-type emitter layer and a gate oxide formed on a surface of the trench gate, and an immunity improving part formed between the trench gates and including a second conductivity-type body layer, a preventing film formed on the surface of the trench gate, and a gate oxide having a thickness less than that the gate oxide of the current increasing part.

    Abstract translation: 提供了一种功率半导体器件，包括形成为彼此间隔开预定距离的多个沟槽栅极，形成在沟槽栅极之间并包括第一导电型发射极层和形成的栅极氧化物的电流增加部分 在所述沟槽栅极的表面上形成的抗扰度改善部以及形成在所述沟槽栅极之间并且包括第二导电型体层的抗扰度改善部，以及形成在所述沟槽栅极的表面上的防止膜和厚度小于所述沟槽栅极的厚度的栅极氧化物。 电流增加部分的栅极氧化物。

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