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公开(公告)号：US20250037744A1
公开(公告)日：2025-01-30
申请号：US18777820
申请日：2024-07-19
Applicant: Renesas Electronics Corporation
Inventor： Toshiki KIRYU , Toma OGATA , Kosuke YAYAMA , Toyohiro SHIMOGAWA
Abstract: While suppressing the influence of voltage noise, the adjustment range of the power supply voltage generated based on the reference voltage is expanded. The semiconductor device includes a reference voltage generation circuit, a regulator, a buffer, and a voltage control circuit. The reference voltage generation circuit is configured to be able to adjust the reference voltage. The regulator is configured to be able to change the output ratio of the power supply voltage to the reference voltage based on the control signal. The semiconductor device further includes a voltage control circuit for outputting a voltage control signal to the regulator to switch the output ratio.
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公开(公告)号：US20210257443A1
公开(公告)日：2021-08-19
申请号：US17154775
申请日：2021-01-21
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Chiemi HASHIMOTO , Kosuke YAYAMA , Hidekazu TAWARA
IPC: H01L49/02 , H01L27/06 , H01L23/522 , H01F7/06 , H03B5/24
Abstract: A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.
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公开(公告)号：US20160139623A1
公开(公告)日：2016-05-19
申请号：US15007842
申请日：2016-01-27
Applicant: Renesas Electronics Corporation
Inventor： Kosuke YAYAMA , Takashi NAKAMURA
IPC: G06F1/08
CPC classification number: G06F1/08 , H01C13/02 , H01L27/0802 , H01L28/20 , H03B5/24
Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.
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公开(公告)号：US20240310863A1
公开(公告)日：2024-09-19
申请号：US18588650
申请日：2024-02-27
Applicant: Renesas Electronics Corporation
Inventor： Atsushi TSUDA , Kosuke YAYAMA
Abstract: A capless regulator circuit is provided. The regulator circuit includes a power transistor that controls the supply of current to an external output terminal connected to a load; a monitor transistor provided between the external output terminal and a reference voltage terminal to which a reference voltage is supplied, and through which a current corresponding to the voltage of the external output terminal flows; a first constant current source that is provided in series with the monitor transistor and generates a first voltage according to the difference between the first current and a first constant current; and a cascode circuit that generates a second voltage that amplifies the first voltage and supplies it to the gate of the power transistor.
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公开(公告)号：US20230195159A1
公开(公告)日：2023-06-22
申请号：US18059147
申请日：2022-11-28
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kosuke YAYAMA
IPC: G06F1/04 , G11C5/14 , H03B5/12 , H03K19/0944
CPC classification number: G06F1/04 , G11C5/145 , H03B5/1284 , H03K19/0944
Abstract: A technique capable of detecting a substrate bias voltage at a low power consumption is provided. The technique including: a voltage boost circuit outputting a boost voltage based on a first clock signal having a first frequency; a voltage drop circuit outputting a drop voltage based on a second clock signal having a second frequency; and a logic circuit block comparing the first frequency and the second frequency and outputting a comparison result between the first frequency and the second frequency in accordance with predetermined criteria is provided.
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Patent Agency Ranking
公开(公告)号：US20160054183A1
公开(公告)日：2016-02-25
申请号：US14805624
申请日：2015-07-22
Applicant: Renesas Electronics Corporation
Inventor： Kosuke YAYAMA
CPC classification number: G01K15/005 , G01K7/01
Abstract: There is provided a semiconductor device which can provide desired output characteristics suitable to applications. A semiconductor device 10 includes a temperature sensing unit 11 which generates an analog sensing signal corresponding to a temperature, and an AD converter unit 12 which converts the analog sensing signal into a digital output signal corresponding to an adjusted temperature change rate based on a temperature change rate adjustment signal for adjusting the temperature change rate. The temperature change rate refers to a change in a detected temperature per bit of a digital output signal.
Abstract translation: 提供了可以提供适合于应用的期望的输出特性的半导体器件。 半导体装置10包括产生对应于温度的模拟感测信号的温度检测单元11以及将模拟感测信号转换为对应于基于温度变化的调节温度变化率的数字输出信号的AD转换单元12 速率调节信号，用于调节温度变化率。 温度变化率是指数字输出信号每位检测温度的变化。
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公开(公告)号：US20200076409A1
公开(公告)日：2020-03-05
申请号：US16534592
申请日：2019-08-07
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Chiemi HASHIMOTO , Kosuke YAYAMA , Tomokazu MATSUZAKI
IPC: H03K3/011 , H01L49/02 , H01L23/522 , G01L1/22
Abstract: The polysilicon resistance has a large resistance variation rate after the end of the mold packaging process. In order to enable high-precision trimming, it is desired to realize a resistance which is hardly affected by stress and temperature fluctuation generated in a substrate by a mold packaging process. A resistance element is formed in a plurality of wiring layers, and has a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of types of materials.
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公开(公告)号：US20180375497A1
公开(公告)日：2018-12-27
申请号：US16004014
申请日：2018-06-08
Applicant: Renesas Electronics Corporation
Inventor： Chiemi HASHIMOTO , Kosuke YAYAMA , Katsumi TSUNENO , Tomokazu MATSUZAKI
IPC: H03K3/011 , H01L27/08 , H01L49/02 , H01L23/522 , H03K3/356
Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.
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公开(公告)号：US20140312981A1
公开(公告)日：2014-10-23
申请号：US14244800
申请日：2014-04-03
Applicant: Renesas Electronics Corporation
Inventor： Takashi NAKAMURA , Kosuke YAYAMA , Masaaki IIJIMA
IPC: H03L7/06
CPC classification number: H03L7/0991 , H03L1/022 , H03L7/00 , H03L7/02 , H03L7/06 , H03L7/099 , H03L7/16 , H03L7/22 , H03L2207/06 , H03L2207/50
Abstract: A frequency-locked loop circuit includes: a digital control oscillator that generates a clock; and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes: a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock; and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit and outputs the frequency control code to the digital control oscillator.
Abstract translation: 锁频环路电路包括：产生时钟的数字控制振荡器; 以及FLL控制器，其生成用于控制时钟的振荡频率的频率控制码。 FLL控制器包括：频率比较单元，其将由数字控制振荡器产生的时钟的频率与相乘的参考时钟的频率进行比较; 以及延迟码控制单元，其基于频率比较单元的比较结果生成频率控制码，使得由数字控制振荡器产生的时钟的频率与倍增的参考时钟的频率相匹配。 频率比较单元通过使用第一和第二阈值来确定时钟的频率。 延迟代码控制单元根据频率比较单元的确定产生频率控制代码，并将频率控制代码输出到数字控制振荡器。
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公开(公告)号：US20180351509A1
公开(公告)日：2018-12-06
申请号：US15928948
申请日：2018-03-22
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Guoqiang ZHANG , Kosuke YAYAMA
CPC classification number: H03B5/04 , H03B5/1206 , H03B5/1228 , H03B5/1231 , H03K3/011 , H03K3/0231 , H03L1/022 , H03L7/00
Abstract: A semiconductor device includes a reference voltage generation circuit configured to generate reference voltages Va and Vb capable of adjusting a primary temperature characteristic, and an oscillation circuit configured to output an oscillation signal using the reference voltages Va and Vb, in which the oscillation circuit includes a frequency/current conversion circuit that is driven by the reference voltage Va and outputs a current Ie in accordance with a frequency of a feedback signal, a control voltage generation circuit configured to generate a control voltage in accordance with a potential difference between a voltage in accordance with the current Ie and the reference voltage Vb, a voltage control oscillation circuit configured to output the oscillation signal having a frequency in accordance with the control voltage, and a frequency division circuit configured to divide a frequency of the oscillation signal and output the resulting signal as the feedback signal.
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