公开(公告)号：US20220216866A1

公开(公告)日：2022-07-07

申请号：US17560671

申请日：2021-12-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Issei KASHIMA ,  Atsushi TSUDA

IPC: H03K17/60 ,  H03K17/687 ,  H03K5/24

Abstract: To provide a technique for detecting a low voltage of a power-on reset circuit. A semiconductor device has a power-on reset circuit including: a first bipolar transistor; a second bipolar transistor formed by connecting a plurality of bipolar transistors in parallel; a detection-voltage adjusting resistance element; a temperature-characteristic adjusting resistance element; a current adjusting resistance element; and a comparator.

公开(公告)号：US20240310863A1

公开(公告)日：2024-09-19

申请号：US18588650

申请日：2024-02-27

Applicant: Renesas Electronics Corporation

Inventor： Atsushi TSUDA ,  Kosuke YAYAMA

IPC: G05F1/565 ,  G05F1/46

CPC classification number: G05F1/565 ,  G05F1/468

Abstract: A capless regulator circuit is provided. The regulator circuit includes a power transistor that controls the supply of current to an external output terminal connected to a load; a monitor transistor provided between the external output terminal and a reference voltage terminal to which a reference voltage is supplied, and through which a current corresponding to the voltage of the external output terminal flows; a first constant current source that is provided in series with the monitor transistor and generates a first voltage according to the difference between the first current and a first constant current; and a cascode circuit that generates a second voltage that amplifies the first voltage and supplies it to the gate of the power transistor.