公开(公告)号：US20200006303A1

公开(公告)日：2020-01-02

申请号：US16444933

申请日：2019-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

公开(公告)号：US20230411368A1

公开(公告)日：2023-12-21

申请号：US18461884

申请日：2023-09-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/165 ,  H01L25/105 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/83 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2224/32225 ,  H01L23/3675

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a wiring substrate, a semiconductor chip and a capacitor mounted on the upper surface of the wiring substrate, and a lid formed of a metallic plate covering the semiconductor chip and the wire in substrate. The semiconductor chip is bonded to the lid via a conductive adhesive layer, and the capacitor, which is thicker than the thickness of the semiconductor chip, is disposed in the cut off portion provided in the lid, and is exposed from the lid.

公开(公告)号：US20170053846A1

公开(公告)日：2017-02-23

申请号：US15220438

申请日：2016-07-27

Applicant: Renesas Electronics Corporation

Inventor： Yosuke KATSURA ,  Yusuke TANUMA

IPC: H01L23/18 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device includes a memory component, which is a semiconductor component (a semiconductor chip or a semiconductor package), to be mounted over an upper surface of a wiring substrate. In addition, in the upper surface, a distance between the memory component and a first substrate side of the upper surface is smaller than a distance between the memory component and a second substrate side of the upper surface. In addition, in the upper surface, a dam portion is formed between the memory component and the first substrate side.

Abstract translation: 半导体器件包括作为半导体部件（半导体芯片或半导体封装）的存储部件，被安装在布线基板的上表面上。 此外，在上表面中，存储部件与上表面的第一基板侧之间的距离小于上表面的存储部件与第二基板侧之间的距离。 此外，在上表面中，在存储部件和第一基板侧之间形成有阻挡部。

公开(公告)号：US20220013508A1

公开(公告)日：2022-01-13

申请号：US17486301

申请日：2021-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

公开(公告)号：US20190363050A1

公开(公告)日：2019-11-28

申请号：US16405644

申请日：2019-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI ,  Kazuyuki NAKAGAWA ,  Keita TSUCHIYA ,  Yosuke KATSURA ,  Shinji KATAYAMA ,  Norio CHUJO ,  Masayoshi YAGYU ,  Yutaka UEMATSU

IPC: H01L23/538 ,  H05K1/02 ,  H04L25/02 ,  H01L23/66 ,  H01L23/498

Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

公开(公告)号：US20170178985A1

公开(公告)日：2017-06-22

申请号：US15333693

申请日：2016-10-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshiaki SATO ,  Yosuke KATSURA

IPC: H01L23/04 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/10

CPC classification number: H01L23/04 ,  H01L21/4817 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/73 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16196 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/3512

Abstract: A semiconductor device includes a semiconductor chip and a package structure mounted on a wiring substrate, and a lid for covering the semiconductor chip, which is fixed to the surface of the wiring substrate, without overlapping with the package structure in plan view. The lid includes an upper surface portion overlapping with the semiconductor chip, a flange portion fixed to the surface of the wiring substrate, and a slant portion for jointing the upper surface portion and the flange portion. Then, a distance from the surface of the wiring substrate to the top surface of the upper surface portion is larger than a distance from the surface of the wiring substrate to the top surface of the flange portion.