公开(公告)号：US20220013508A1

公开(公告)日：2022-01-13

申请号：US17486301

申请日：2021-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

公开(公告)号：US20200006303A1

公开(公告)日：2020-01-02

申请号：US16444933

申请日：2019-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

公开(公告)号：US20180294239A1

公开(公告)日：2018-10-11

申请号：US15888846

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Kenji SAKATA ,  Toshihiko AKIBA ,  Takuo FUNAYA ,  Hideaki TSUCHIYA ,  Yuichi YOSHIDA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: There is a need to improve reliability of the semiconductor device.A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.

公开(公告)号：US20170278722A1

公开(公告)日：2017-09-28

申请号：US15621226

申请日：2017-06-13

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko AKIBA ,  Hiromi SHIGIHARA ,  Kei YAJIMA

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/525

CPC classification number: H01L21/4889 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/525 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.

公开(公告)号：US20230411368A1

公开(公告)日：2023-12-21

申请号：US18461884

申请日：2023-09-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/165 ,  H01L25/105 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/83 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2224/32225 ,  H01L23/3675

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a wiring substrate, a semiconductor chip and a capacitor mounted on the upper surface of the wiring substrate, and a lid formed of a metallic plate covering the semiconductor chip and the wire in substrate. The semiconductor chip is bonded to the lid via a conductive adhesive layer, and the capacitor, which is thicker than the thickness of the semiconductor chip, is disposed in the cut off portion provided in the lid, and is exposed from the lid.

公开(公告)号：US20220165638A1

公开(公告)日：2022-05-26

申请号：US17517908

申请日：2021-11-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Yusuke TANUMA

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/04 ,  H01L23/00

Abstract: A semiconductor device includes: a wiring substrate; a semiconductor chip mounted on the wiring substrate; a heat release sheet arranged on the semiconductor chip to cover the entire semiconductor chip and having a larger area than an area of the semiconductor chip; and a cover member which covers the semiconductor chip and the heat release sheet and to which the heat release sheet is fixed. The cover member has a first portion facing the semiconductor chip, a flange portion arranged in a periphery of the first portion and bonded and fixed onto the wiring substrate, and a second portion arranged between the first portion and the flange portion. In a plan view of the cover member viewed from the heat release sheet, the heat release sheet is bonded/fixed to the cover member through a bonding member partially arranged between the heat release sheet and the cover member.

公开(公告)号：US20180158771A1

公开(公告)日：2018-06-07

申请号：US15721784

申请日：2017-09-30

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko AKIBA ,  Shuuichi KARIYAZAKI

IPC: H01L23/528 ,  H01L23/15 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/4901 ,  H01L2224/494 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.

公开(公告)号：US20160197050A1

公开(公告)日：2016-07-07

申请号：US15071545

申请日：2016-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Akihiro TOBITA ,  Yuki YAGYU

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/05 ,  H01L21/4885 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05555 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05673 ,  H01L2224/05684 ,  H01L2224/16012 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8501 ,  H01L2224/85375 ,  H01L2224/97 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.

公开(公告)号：US20160133484A1

公开(公告)日：2016-05-12

申请号：US14886088

申请日：2015-10-18

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko AKIBA ,  Hiromi SHIGIHARA ,  Kei YAJIMA

IPC: H01L21/48

CPC classification number: H01L21/4889 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/525 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.

Abstract translation: 提供了可以实现尺寸减小的可靠性提高的半导体器件。 提供一种半导体晶片，其具有第一绝缘构件，该第一绝缘构件具有暴露于电极焊盘的上表面的开口。 随后，在半导体晶片的主表面上形成第二绝缘构件之后，形成另一个开口以露出电极焊盘的上表面。 然后，使探针与电极焊盘接触，将数据写入半导体晶片的主表面的存储电路。 在用导电覆盖膜覆盖电极焊盘的上表面之后，形成重定位布线。 在Y方向上，位于电极焊盘正上方的位移线的宽度等于或小于形成在第一绝缘构件中的开口的宽度。

公开(公告)号：US20150333030A1

公开(公告)日：2015-11-19

申请号：US14711014

申请日：2015-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Akihiro TOBITA ,  Yuki YAGYU

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/4885 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05555 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05673 ,  H01L2224/05684 ,  H01L2224/16012 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8501 ,  H01L2224/85375 ,  H01L2224/97 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.

Abstract translation: 一种BGA的制造方法，包括以下步骤：提供具有电极焊盘的半导体芯片; 并除去形成在每个电极焊盘的表面上的自然氧化膜。 此外，在通过去除天然氧化物膜而暴露的电极焊盘的表面上形成由导电部件构成的第一膜，电线与第一膜连接，并且电线的一部分与电极焊盘接触， 在导线和电极焊盘之间的界面处形成合金层。 第一膜的晶体结构由体心立方晶格或六方密堆积晶格组成。 可以降低半导体器件的成本，同时确保半导体器件的引线接合的接合可靠性。