公开(公告)号：US20160300597A1

公开(公告)日：2016-10-13

申请号：US15190263

申请日：2016-06-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada FUNANE ,  Ken SHIBATA ,  Yasuhisa SHIMAZAKI

IPC: G11C5/06

CPC classification number: G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US20130258741A1

公开(公告)日：2013-10-03

申请号：US13900127

申请日：2013-05-22

Applicant: Renesas Electronics Corporation

Inventor： Kiyotada FUNANE ,  Ken SHIBATA ,  Yasuhisa SHIMAZAKI

IPC: G11C5/02

CPC classification number: G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US20170236576A1

公开(公告)日：2017-08-17

申请号：US15583093

申请日：2017-05-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada FUNANE ,  Ken SHIBATA ,  Yasuhisa SHIMAZAKI

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US20150003140A1

公开(公告)日：2015-01-01

申请号：US14490235

申请日：2014-09-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada FUNANE ,  Ken SHIBATA ,  Yasuhisa SHIMAZAKI

IPC: G11C5/02

CPC classification number: G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

Abstract translation: 能够扩大噪声容限的半导体器件。 例如，在存储单元MC与第一端口的字线WLA和第二端口的字线WLB连接的存储区域中，并且多个存储单元MC以矩阵形状配置， 线以WLA0，WLB0，WLB1，WLA1，WLA2的顺序排列。 此外，使WLA-WLA和WLB-WLB之间的间距d2小于WLA-WLB之间的间距d1。 这样，相同端口的字线以某一字线的两侧之一的间距d2设置，而不同端口的字线以间距d1设置。

公开(公告)号：US20170287918A1

公开(公告)日：2017-10-05

申请号：US15631604

申请日：2017-06-23

Applicant: Renesas Electronics Corporation

Inventor： Kiyotada FUNANE

IPC: H01L27/11 ,  G11C11/419 ,  H01L23/528 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L27/1104 ,  G11C5/063 ,  G11C5/14 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

公开(公告)号：US20160372477A1

公开(公告)日：2016-12-22

申请号：US15251504

申请日：2016-08-30

Applicant: Renesas Electronics Corporation

Inventor： Kiyotada FUNANE

IPC: H01L27/11 ,  G11C11/418 ,  G11C11/419 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/1104 ,  G11C5/063 ,  G11C5/14 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

公开(公告)号：US20160049368A1

公开(公告)日：2016-02-18

申请号：US14918788

申请日：2015-10-21

Applicant: Renesas Electronics Corporation

Inventor： Kiyotada FUNANE

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L27/1104 ,  G11C5/063 ,  G11C5/14 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

公开(公告)号：US20130221538A1

公开(公告)日：2013-08-29

申请号：US13774453

申请日：2013-02-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada FUNANE

IPC: H01L23/48

CPC classification number: H01L27/1104 ,  G11C5/063 ,  G11C5/14 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

公开(公告)号：US20190147940A1

公开(公告)日：2019-05-16

申请号：US16250275

申请日：2019-01-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada FUNANE ,  Ken SHIBATA ,  Yasuhisa SHIMAZAKI

IPC: G11C11/417 ,  H01L27/11 ,  H01L27/02 ,  G11C11/413 ,  G11C7/10 ,  G11C8/16 ,  G11C5/06 ,  G11C5/02 ,  G11C11/412

CPC classification number: G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US20180350822A1

公开(公告)日：2018-12-06

申请号：US16100857

申请日：2018-08-10

Applicant: Renesas Electronics Corporation

Inventor： Kiyotada FUNANE

IPC: H01L27/11 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  G11C11/419 ,  G11C11/418 ,  G11C11/417 ,  G11C5/14 ,  G11C5/06

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.