公开(公告)号：US20200083167A1

公开(公告)日：2020-03-12

申请号：US16123429

申请日：2018-09-06

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Eduardo M. Chumbes ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778

Abstract: A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.

公开(公告)号：US20190237554A1

公开(公告)日：2019-08-01

申请号：US16381485

申请日：2019-04-11

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior ,  Kamal Tabatabaie Alavi

IPC: H01L29/40 ,  H01L23/48 ,  H01L29/20 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L21/285 ,  H01L23/535 ,  H01L23/485

CPC classification number: H01L29/404 ,  H01L21/28114 ,  H01L21/28575 ,  H01L21/28587 ,  H01L23/481 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/535 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2229/00

Abstract: A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.

公开(公告)号：US20180240753A1

公开(公告)日：2018-08-23

申请号：US15438148

申请日：2017-02-21

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Eduardo M. Chumbes ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/20 ,  H01L21/324 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53271 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/452

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

公开(公告)号：US09761445B2

公开(公告)日：2017-09-12

申请号：US15082500

申请日：2016-03-28

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L29/20 ,  H01L21/02 ,  H01L21/762 ,  H01L23/66 ,  H01L21/683 ,  H01L21/8258 ,  H01P11/00

CPC classification number: H01L21/0254 ,  H01L21/6835 ,  H01L21/7605 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/8258 ,  H01L23/66 ,  H01L29/2003 ,  H01L2221/68327 ,  H01L2224/32145 ,  H01L2924/0002 ,  H01P11/003 ,  H01L2924/00

Abstract: A method for providing a semiconductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

公开(公告)号：US20230073459A1

公开(公告)日：2023-03-09

申请号：US18049368

申请日：2022-10-25

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior ,  Eduardo M. Chumbes

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/08 ,  H01L29/20 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

公开(公告)号：US20190165108A1

公开(公告)日：2019-05-30

申请号：US15827349

申请日：2017-11-30

Applicant: RAYTHEON COMPANY

Inventor： Hooman Kazemi ,  Mark Rosker ,  Thomas E. Kazior ,  Shane A. O'Connor ,  Emily Elswick

IPC: H01L29/20 ,  H01L23/482 ,  H01L23/538 ,  H01L23/552 ,  H01L23/29

Abstract: A reconstituted wafer includes a plurality of apertures defined in a first substrate. A module is positioned in each aperture and coupled to circuit traces on the first substrate by operation of beam leads extending from the module. A second substrate is positioned over the first substrate and each module is hermetically sealed in a space defined by the respective aperture and the second substrate. One or more vias are provided to access I/O signals at a surface of the first or second substrates. The modules may include an invariant die where different technologies are stacked together.

公开(公告)号：US10096550B2

公开(公告)日：2018-10-09

申请号：US15438196

申请日：2017-02-21

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Eduardo M. Chumbes ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L29/778 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3213

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

公开(公告)号：US20180240754A1

公开(公告)日：2018-08-23

申请号：US15438196

申请日：2017-02-21

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Eduardo M. Chumbes ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L23/535 ,  H01L29/778 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/535 ,  H01L21/32134 ,  H01L21/76895 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

公开(公告)号：US11784248B2

公开(公告)日：2023-10-10

申请号：US18049368

申请日：2022-10-25

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior ,  Eduardo M. Chumbes

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/08 ,  H01L29/20 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/04 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462

Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

公开(公告)号：US20200219982A1

公开(公告)日：2020-07-09

申请号：US16821559

申请日：2020-03-17

Applicant: RAYTHEON COMPANY

Inventor： Hooman Kazemi ,  Mark Rosker ,  Thomas E. Kazior ,  Shane A. O'Connor ,  Emily Elswick

IPC: H01L29/20 ,  H01L23/482 ,  H01L23/29 ,  H01L23/552 ,  H01L23/538

Abstract: A reconstituted wafer includes a plurality of apertures defined in a first substrate. A module is positioned in each aperture and coupled to circuit traces on the first substrate by operation of beam leads extending from the module. A second substrate is positioned over the first substrate and each module is enclosed in a space defined by the respective aperture and the second substrate. The module includes a lid and at least one mode suppression circuit disposed in the lid. The modules may include an invariant die where different technologies are stacked together.