公开(公告)号：US09461040B2

公开(公告)日：2016-10-04

申请号：US14792363

申请日：2015-07-06

Applicant: QUALCOMM Incorporated

Inventor： Ming Cai ,  Samit Sengupta ,  Chock Hing Gan ,  PR Chidambaram

IPC: H01L21/00 ,  H01L21/66 ,  H01L27/00 ,  H01L29/00 ,  G06F17/50 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/088 ,  G06F17/5068 ,  H01L21/28035 ,  H01L21/823456 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0207 ,  H01L29/4916

Abstract: A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.

Abstract translation: 一种方法包括形成第一晶体管的第一栅极，第一栅极具有第一长度。 第一晶体管位于第一芯中。 该方法还包括形成第二晶体管的第二栅极，第二栅极具有比第一长度短的第二长度。 第二晶体管位于第二核心中。 第一芯位于比第二芯更靠近半导体晶粒的中心的位置。 第二晶体管和第一晶体管是相应的晶体管。

公开(公告)号：US20150311198A1

公开(公告)日：2015-10-29

申请号：US14792363

申请日：2015-07-06

Applicant: QUALCOMM INCORPORATED

Inventor： Ming Cai ,  Samit Sengupta ,  Chock Hing Gan ,  PR Chidambaram

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  G06F17/5068 ,  H01L21/28035 ,  H01L21/823456 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0207 ,  H01L29/4916

Abstract: A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.

Abstract translation: 一种方法包括形成第一晶体管的第一栅极，第一栅极具有第一长度。 第一晶体管位于第一芯中。 该方法还包括形成第二晶体管的第二栅极，第二栅极具有比第一长度短的第二长度。 第二晶体管位于第二核心中。 第一芯位于比第二芯更靠近半导体晶粒的中心的位置。 第二晶体管和第一晶体管是相应的晶体管。

公开(公告)号：US20150061037A1

公开(公告)日：2015-03-05

申请号：US14017635

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Ming Cai ,  Samit Sengupta ,  Chock Hing Gan ,  PR Chidambaram

IPC: H01L29/49 ,  G06F17/50 ,  H01L21/66 ,  H01L21/28

CPC classification number: H01L27/088 ,  G06F17/5068 ,  H01L21/28035 ,  H01L21/823456 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0207 ,  H01L29/4916

Abstract: A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.

Abstract translation: 一种方法包括形成第一晶体管的第一多晶硅栅极，第一多晶硅栅极具有第一长度。 第一晶体管位于第一芯中。 该方法还包括形成第二晶体管的第二多晶硅栅极，第二多晶硅栅极具有比第一长度短的第二长度。 第二晶体管位于第二核心中。 第一芯位于比第二芯更靠近半导体晶粒的中心的位置。

公开(公告)号：US09245971B2

公开(公告)日：2016-01-26

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  P R Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/8238

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间。

公开(公告)号：US09076775B2

公开(公告)日：2015-07-07

申请号：US14017635

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Ming Cai ,  Samit Sengupta ,  Chock Hing Gan ,  PR Chidambaram

IPC: H01L27/088 ,  H01L21/70 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/28 ,  G06F17/50 ,  H01L21/66

CPC classification number: H01L27/088 ,  G06F17/5068 ,  H01L21/28035 ,  H01L21/823456 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0207 ,  H01L29/4916

Abstract: A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.

Abstract translation: 一种方法包括形成第一晶体管的第一多晶硅栅极，第一多晶硅栅极具有第一长度。 第一晶体管位于第一芯中。 该方法还包括形成第二晶体管的第二多晶硅栅极，第二多晶硅栅极具有比第一长度短的第二长度。 第二晶体管位于第二核心中。 第一芯位于比第二芯更靠近半导体晶粒的中心的位置。

公开(公告)号：US20150091060A1

公开(公告)日：2015-04-02

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  PR Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间

公开(公告)号：US10853542B1

公开(公告)日：2020-12-01

申请号：US16442347

申请日：2019-06-14

Applicant: QUALCOMM Incorporated

Inventor： Samit Sengupta ,  Anil Chowdary Kota ,  Fadoua Chafik

IPC: G06F17/50 ,  G01R31/00 ,  G06F30/327 ,  G06F30/33 ,  G06F30/34 ,  G06F30/3323 ,  G01R31/3183

Abstract: A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

公开(公告)号：US20180350819A1

公开(公告)日：2018-12-06

申请号：US15609505

申请日：2017-05-31

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung Choi ,  Samit Sengupta ,  Shashank Ekbote

IPC: H01L27/11 ,  H01L29/10 ,  H01L23/528 ,  H01L27/092 ,  H01L23/532 ,  H01L29/49 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/0207

Abstract: Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail to distribute a first supply voltage to a Pwell region of corresponding SRAM bit cell rows. The SRAM strap cell also includes an N-type doped well (Nwell) tap electrically coupled to a second supply rail to distribute a second supply voltage to an Nwell region of corresponding SRAM bit cell rows. In one exemplary aspect, the Nwell tap can include multiple supply contacts used to couple the second supply rail to the SRAM strap cell to reduce mechanical stress in the Nwell tap. In another exemplary aspect, the Pwell tap can include non-active gates disposed across multiple Fins to stabilize the Fins and reduce or avoid mechanical stress in the Pwell tap.