公开(公告)号：US10853542B1

公开(公告)日：2020-12-01

申请号：US16442347

申请日：2019-06-14

Applicant: QUALCOMM Incorporated

Inventor： Samit Sengupta ,  Anil Chowdary Kota ,  Fadoua Chafik

IPC: G06F17/50 ,  G01R31/00 ,  G06F30/327 ,  G06F30/33 ,  G06F30/34 ,  G06F30/3323 ,  G01R31/3183

Abstract: A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.