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公开(公告)号：US09798376B2
公开(公告)日：2017-10-24
申请号：US14817178
申请日：2015-08-03
Applicant: QUALCOMM Incorporated
Inventor： Dipti Ranjan Pal
CPC classification number: G06F1/324 , G06F1/08 , G06F1/3237 , G06F1/3243 , Y02D10/126 , Y02D10/128 , Y02D10/152
Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In one embodiment, a method for activating one or more processors comprises reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors. The method also comprises activating the one or more processors after the frequency of the clock signal is reduced, and increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.
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公开(公告)号：US20150355671A1
公开(公告)日：2015-12-10
申请号：US14300084
申请日：2014-06-09
Applicant: QUALCOMM Incorporated
Inventor： Ryan Michael Coutts , Dipti Ranjan Pal
IPC: G06F1/08
CPC classification number: G06F1/08 , G06F1/206 , G06F1/324 , H03K21/026 , H03K23/662 , H03L1/022 , Y02D10/126 , Y02D10/16
Abstract: Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.
Abstract translation: 这里描述了通过选择性地吞咽时钟信号中的脉冲来控制时钟信号的频率的系统和方法。 在一个实施例中，一种用于调整时钟信号的频率的方法包括：根据重复的时钟吞咽模式接收时钟信号和吞咽时钟信号中的脉冲，其中，所述模式由数字序列定义。
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公开(公告)号：US11880454B2
公开(公告)日：2024-01-23
申请号：US16874538
申请日：2020-05-14
Applicant: QUALCOMM Incorporated
Inventor： Bharat Kumar Rangarajan , Dipti Ranjan Pal , Keith Alan Bowman , Srinivas Turaga , Ateesh Deepankar De , Shih-Hsin Jason Hu , Chandan Agarwalla
CPC classification number: G06F21/554 , G06F1/26 , G06F2221/034
Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.
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公开(公告)号：US11855645B2
公开(公告)日：2023-12-26
申请号：US17485361
申请日：2021-09-25
Applicant: QUALCOMM Incorporated
Inventor： Keith Alan Bowman , Daniel Yingling , Dipti Ranjan Pal
CPC classification number: H03K5/1565 , H03K3/017 , H03L7/0814
Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.
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公开(公告)号：US10014869B1
公开(公告)日：2018-07-03
申请号：US15453712
申请日：2017-03-08
Applicant: QUALCOMM Incorporated
Inventor： Kevin Bowles , Dipti Ranjan Pal
CPC classification number: H03L7/1974 , H03K3/017 , H03K21/10 , H03K2005/00013 , H03L7/085
Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.
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Patent Agency Ranking
公开(公告)号：US11493970B2
公开(公告)日：2022-11-08
申请号：US17085505
申请日：2020-10-30
Applicant: QUALCOMM INCORPORATED
Inventor： Christopher Kong Yee Chun , Chandan Agarwalla , Dipti Ranjan Pal , Kumar Kanti Ghosh , Matthew Severson , Nilanjan Banerjee , Joshua Stubbs
IPC: G06F1/26 , G06F1/3296 , G06F1/3228 , G06F1/3287
Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.
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公开(公告)号：US11424736B1
公开(公告)日：2022-08-23
申请号：US17485357
申请日：2021-09-25
Applicant: QUALCOMM Incorporated
Inventor： Keith Alan Bowman , Daniel Yingling , Dipti Ranjan Pal
Abstract: Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.
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公开(公告)号：US10915157B2
公开(公告)日：2021-02-09
申请号：US16276532
申请日：2019-02-14
Applicant: QUALCOMM Incorporated
Inventor： Dipti Ranjan Pal , Jeffrey Gemar , Abinash Roy
IPC: G06F1/00 , G06F1/324 , G06F1/08 , G06F1/3237 , G06F1/3203
Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.
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公开(公告)号：US10386904B2
公开(公告)日：2019-08-20
申请号：US15086054
申请日：2016-03-31
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward Podaima , Christophe Denis Bernard Avoinne , Manokanthan Somasundaram , Sina Dena , Paul Christopher John Wiercienski , Bohuslav Rychlik , Steven John Halter , Jaya Prakash Subramaniam Ganasan , Myil Ramkumar , Dipti Ranjan Pal
IPC: G06F1/26 , G06F1/10 , G06F1/324 , G06F1/3234 , G06F1/3287 , G06F12/08
Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
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公开(公告)号：US10250270B2
公开(公告)日：2019-04-02
申请号：US15987208
申请日：2018-05-23
Applicant: QUALCOMM Incorporated
Inventor： Kevin Bowles , Dipti Ranjan Pal
Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.
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