公开(公告)号：US11424736B1

公开(公告)日：2022-08-23

申请号：US17485357

申请日：2021-09-25

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan Bowman ,  Daniel Yingling ,  Dipti Ranjan Pal

IPC: H03K3/017 ,  H03K19/20 ,  H03K5/01 ,  G06F1/10 ,  H03K5/00

Abstract: Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.

公开(公告)号：US12224752B1

公开(公告)日：2025-02-11

申请号：US18354374

申请日：2023-07-18

Applicant: QUALCOMM Incorporated

Inventor： Yimai Peng ,  Robert Joseph Vachon ,  Daniel Yingling ,  Keith Alan Bowman

IPC: G06F1/04 ,  H03K3/037 ,  H03K17/00 ,  H03K19/21

Abstract: An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

公开(公告)号：US11855645B2

公开(公告)日：2023-12-26

申请号：US17485361

申请日：2021-09-25

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan Bowman ,  Daniel Yingling ,  Dipti Ranjan Pal

IPC: H03K5/156 ,  H03K3/017 ,  H03L7/081

CPC classification number: H03K5/1565 ,  H03K3/017 ,  H03L7/0814

Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

公开(公告)号：US11270761B2

公开(公告)日：2022-03-08

申请号：US17223764

申请日：2021-04-06

Applicant: Qualcomm Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Daniel Yingling ,  Jihoon Jeong ,  Yu Pu

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

公开(公告)号：US10978139B2

公开(公告)日：2021-04-13

申请号：US16431503

申请日：2019-06-04

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Daniel Yingling ,  Jihoon Jeong ,  Yu Pu

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/10 ,  G11C11/417 ,  G11C11/419 ,  G11C11/418

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.