公开(公告)号：US11733767B2

公开(公告)日：2023-08-22

申请号：US17359350

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar Kakkireni ,  Matthew Severson ,  Kumar Kanti Ghosh ,  Shishir Joshi

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  H04L12/10

CPC classification number: G06F1/3296 ,  H04L12/10

Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

公开(公告)号：US11493970B2

公开(公告)日：2022-11-08

申请号：US17085505

申请日：2020-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Kong Yee Chun ,  Chandan Agarwalla ,  Dipti Ranjan Pal ,  Kumar Kanti Ghosh ,  Matthew Severson ,  Nilanjan Banerjee ,  Joshua Stubbs

IPC: G06F1/26 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/3287

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

公开(公告)号：US11221667B1

公开(公告)日：2022-01-11

申请号：US16944070

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Venkatesh Ravipati ,  Venkata Biswanath Devarasetty ,  Nirav Narendra Desai ,  Lakshmi Narayana Panuku ,  Kumar Kanti Ghosh ,  Sharath Kumar Nagilla ,  Sravan Kumar Ambapuram ,  Shrikanth Shenoy

IPC: G06F1/32 ,  G06F1/3296

Abstract: An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

公开(公告)号：US20170010320A1

公开(公告)日：2017-01-12

申请号：US14796185

申请日：2015-07-10

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal ,  Kumar Kanti Ghosh

IPC: G01R31/28

CPC classification number: G01R31/2834 ,  G01R31/318505 ,  G01R31/318594

Abstract: A method and apparatus for testing an electronic component is provided. The method begins when a design-for-test (DFT) mode is entered and at least one sensor is enabled. Sensor results are monitored and determine the number of cores or capture domains that may be tested simultaneously. The sensors include a voltage and temperature sensor, and either or both sensors may be enabled during testing. Maximum and minimum voltage levels for each capture domain determine at what value a voltage drop occurs. The number of cores selected minimizes a voltage drop across the electronic component. Maximum and minimum temperatures across the multiple cores of the electronic component determine the number of clocks that may be operated simultaneously during testing. An apparatus includes an electronic device to be tested, test sensors on the electronic device, and an interface to a test fixture.

Abstract translation: 提供了一种用于测试电子部件的方法和装置。 当输入设计测试（DFT）模式并启用至少一个传感器时，该方法开始。 监测传感器结果，并确定可同时测试的核心或捕获区域的数量。 传感器包括电压和温度传感器，并且在测试期间可以启用任一个或两个传感器。 每个捕获域的最大和最小电压电平都决定了发生电压降的值。 所选择的核心数量使得电子部件上的电压降最小化。 电子元件的多个核心的最大和最小温度决定了在测试期间可同时运行的时钟数。 一种装置包括待测试的电子设备，电子设备上的测试传感器以及与测试夹具的接口。