公开(公告)号：US11733767B2

公开(公告)日：2023-08-22

申请号：US17359350

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar Kakkireni ,  Matthew Severson ,  Kumar Kanti Ghosh ,  Shishir Joshi

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  H04L12/10

CPC classification number: G06F1/3296 ,  H04L12/10

Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.