公开(公告)号：US11493970B2

公开(公告)日：2022-11-08

申请号：US17085505

申请日：2020-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Kong Yee Chun ,  Chandan Agarwalla ,  Dipti Ranjan Pal ,  Kumar Kanti Ghosh ,  Matthew Severson ,  Nilanjan Banerjee ,  Joshua Stubbs

IPC: G06F1/26 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/3287

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

公开(公告)号：US20220100248A1

公开(公告)日：2022-03-31

申请号：US17037984

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Naveen Kumar Narala ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun

IPC: G06F1/28 ,  G06F13/36

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

公开(公告)号：US10521392B2

公开(公告)日：2019-12-31

申请号：US15966687

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Mohit Kishore Prasad ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/20 ,  G06F13/16 ,  G06F13/10

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

公开(公告)号：US20180232324A1

公开(公告)日：2018-08-16

申请号：US15864871

申请日：2018-01-08

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun ,  Mohit Prasad ,  Chris Rosolowski

IPC: G06F13/12 ,  G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F15/78

CPC classification number: G06F13/126 ,  G06F13/364 ,  G06F13/385 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7817 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

公开(公告)号：US20170171081A1

公开(公告)日：2017-06-15

申请号：US14966844

申请日：2015-12-11

Applicant: QUALCOMM Incorporated

Inventor： Lalan Mishra ,  Christopher Kong Yee Chun ,  Chiew-Guan Tan ,  Gordon Lee ,  Todd Sutton

IPC: H04L12/801 ,  H04W52/02 ,  H04W28/02 ,  H04L5/14 ,  H04L12/933

CPC classification number: H04L47/12 ,  G06F13/4278 ,  G06F13/4295 ,  H04L5/14 ,  H04L49/109 ,  H04W28/0221 ,  H04W52/0229 ,  Y02D70/122 ,  Y02D70/26

Abstract: System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

公开(公告)号：US20240206066A1

公开(公告)日：2024-06-20

申请号：US18069004

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Kong Yee Chun ,  Mid Deng ,  John Eaton

IPC: H05K1/14 ,  H01R12/71 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01R12/714 ,  H05K3/3442 ,  H05K3/368

Abstract: A hybrid circuit board device includes a hybrid circuit board with a second, child circuit board disposed into a recessed circuit board portion of a first, parent circuit board to combine functionality of the child circuit board and the parent circuit board without exceeding a maximum circuit board height. The parent circuit board includes a first circuit board portion having a first thickness in a thickness direction. First interconnects on the first circuit board portion can couple to a first IC component. The child circuit board includes second interconnects to couple a second IC component. The child circuit board is in the recessed circuit board portion and is coupled to the parent circuit board by at least one board interconnect. The recessed circuit board portion of the parent circuit board has a second thickness that is thinner, in the thickness direction, than the first thickness.

公开(公告)号：US10169274B1

公开(公告)日：2019-01-01

申请号：US15618062

申请日：2017-06-08

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Kong Yee Chun ,  Chris Rosolowski

IPC: G06F13/40 ,  G06F13/364 ,  G06F1/26 ,  G06F3/06 ,  G06F13/42

Abstract: Systems and methods are disclosed resetting a slave identification (SID) of an integrated circuit (IC). An exemplary method comprises determining that a plurality of ICs in communication with a shared bus have the same SID, the shared bus operating in a master/slave configuration. A common memory address of the ICs is identified, where data stored in the common memory address is different for a first IC and a second IC. Each of the ICs receives over the shared bus a new SID value and match data. The ICs compare the match data with the data stored in the common memory address. If the match data is the same as the data in the common memory address, the SID is changed the received new SID value.

公开(公告)号：US10545897B2

公开(公告)日：2020-01-28

申请号：US16106118

申请日：2018-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Kong Yee Chun ,  Chris Rosolowski

IPC: G06F13/362 ,  G06F13/42 ,  G06F1/28

Abstract: Systems and methods are disclosed method for operating a serial interconnect of a computer system in a time deterministic manner. An exemplary method comprises that a command to be sent over the serial interconnect in a transaction is to be executed at a specific time. A delay period for the command to be sent from a master of the computer system to a slave of the computer system via the serial bus is determined, where the delay period determined based on a length of an arbitration phase of the transaction. The command is then sent to the slave of the computer system via the serial bus after the delay period.

公开(公告)号：US09973431B2

公开(公告)日：2018-05-15

申请号：US14966844

申请日：2015-12-11

Applicant: QUALCOMM Incorporated

Inventor： Lalan Mishra ,  Christopher Kong Yee Chun ,  Chiew-Guan Tan ,  Gordon Lee ,  Todd Sutton

IPC: H04L1/00 ,  H04L12/801 ,  H04L5/14 ,  H04L12/933 ,  H04W28/02 ,  H04W52/02

CPC classification number: H04L47/12 ,  G06F13/4278 ,  G06F13/4295 ,  H04L5/14 ,  H04L49/109 ,  H04W28/0221 ,  H04W52/0229 ,  Y02D70/122 ,  Y02D70/26

Abstract: System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

公开(公告)号：US09634486B2

公开(公告)日：2017-04-25

申请号：US14327410

申请日：2014-07-09

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Yuancheng Christopher Pan ,  Christopher Kong Yee Chun

IPC: G06F1/28 ,  H02J3/00 ,  H02J1/00 ,  H02J1/10

CPC classification number: H02J3/00 ,  G06F1/28 ,  H02J1/00 ,  H02J1/08 ,  H02J1/102

Abstract: Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.