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    Device and method of digital gain programming using sigma-delta modulator
    1.
    发明授权
    Device and method of digital gain programming using sigma-delta modulator 有权

    公开(公告)号：US06804291B1

    公开(公告)日：2004-10-12

    申请号：US09510085

    申请日：2000-02-22

    Applicant: Prakash Easwaran ,  Mrinal Das

    Inventor： Prakash Easwaran ,  Mrinal Das

    IPC: H04B138

    CPC classification number: H03M7/3015 ,  H03M7/3026 ,  H03M7/304

    Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.

    Device and method of digital gain programming using sigma-delta modulator
    2.
    发明授权
    Device and method of digital gain programming using sigma-delta modulator 有权
    使用Σ-Δ调制器的数字增益编程的器件和方法

    公开(公告)号：US06914546B2

    公开(公告)日：2005-07-05

    申请号：US10837092

    申请日：2004-04-29

    Applicant: Prakash Easwaran ,  Mrinal Das

    Inventor： Prakash Easwaran ,  Mrinal Das

    IPC: H03M1/18 ,  H03M3/00 ,  H03M7/38 ,  H04B1/38

    CPC classification number: H03M7/3015 ,  H03M7/3026 ,  H03M7/304

    Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.

    Abstract translation: 可以在调制解调器（120）的数模（DAC）部分（144）中使用Σ-Δ调制器（350）以实现期望的增益编程级别。 利用一组步进系数（GP2，GP4）来确定步长，从而确定调制器（350）的整体增益。 反馈路径被提供和配置为将调制器的输出传递到增益控制块（355），增益控制块（355）在整个传输带宽上提供控制和稳定性。 提供了多级数字输出（320），其表示数字域中的信号电平，并且减少了实现特定增益量所需的离散组件的数量。

    High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same
    3.
    发明申请
    High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same 有权
    具有双向阻挡能力的高压碳化硅器件及其制造方法

    公开(公告)号：US20060261348A1

    公开(公告)日：2006-11-23

    申请号：US11159972

    申请日：2005-06-23

    Applicant: Sei-Hyung Ryu ,  Jason Jenny ,  Mrinal Das ,  Anant Agarwal ,  John Palmour ,  Hudson Hobgood

    Inventor： Sei-Hyung Ryu ,  Jason Jenny ,  Mrinal Das ,  Anant Agarwal ,  John Palmour ,  Hudson Hobgood

    IPC: H01L31/0312

    CPC classification number: H01L29/66068 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/747 ,  H01L29/87 ,  H01L2924/10156

    Abstract: High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer, has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface of the voltage blocking SiC substrate. A third region of SiC is provided on the second SiC layer and has the second conductivity type. A fourth region of SiC is provided in the second SiC layer, has the first conductivity type and is adjacent to the third region of SiC. First and second contacts are provided on the first and third regions of SiC, respectively. Related methods of fabricating high voltage SiC devices are also provided.

    Abstract translation: 提供高压碳化硅（SiC）器件，例如晶闸管。 具有第一导电类型的第一SiC层设置在具有第二导电类型的压电SiC衬底的第一表面上。 SiC的第一区域设置在第一SiC层上并具有第二导电类型。 SiC的第二区域设置在第一SiC层中，具有第一导电类型并且与SiC的第一区域相邻。 具有第一导电类型的第二SiC层设置在压电SiC衬底的第二表面上。 SiC的第三区域设置在第二SiC层上并具有第二导电类型。 SiC的第四区域设置在第二SiC层中，具有第一导电类型并且与SiC的第三区域相邻。 第一和第二触点分别设置在SiC的第一和第三区域上。 还提供了制造高电压SiC器件的相关方法。

    Method and system for signal dependent boosting in sampling circuits
    5.
    发明授权
    Method and system for signal dependent boosting in sampling circuits 有权
    采样电路中信号相关升压的方法和系统

    公开(公告)号：US06833753B2

    公开(公告)日：2004-12-21

    申请号：US10306073

    申请日：2002-11-27

    Applicant: Mrinal Das

    Inventor： Mrinal Das

    IPC: G05F302

    CPC classification number: H02M3/07

    Abstract: A system for signal boosting includes a capacitance boosting component that contains a first and second transistor and a capacitor, wherein a positive terminal of the capacitor is electrically connected to a drain of the second transistor and a negative terminal of the capacitor is electrically connected to a source of the first transistor. The system also includes a third transistor operable to receive a clock signal. A drain of the third transistor is electrically connected to the positive terminal of the capacitor. A fourth transistor is operable to receive an inverse of the clock signal. A drain of the fourth transistor is electrically connected to the positive terminal of the capacitor. The system further includes a boost component electrically connected to the capacitance boosting component wherein an output of the boost component is within a selected boost voltage range.

    Abstract translation: 一种用于信号升压的系统包括一个包含第一和第二晶体管和一个电容器的电容提升元件，其中电容器的正极电连接到第二晶体管的漏极，电容器的负极电连接到 第一晶体管的源极。 该系统还包括可操作以接收时钟信号的第三晶体管。 第三晶体管的漏极与电容器的正极电连接。 第四晶体管可操作以接收时钟信号的反相。 第四晶体管的漏极与电容器的正极电连接。 该系统还包括电连接到电容增压组件的升压组件，其中升压组件的输出在选定的升压电压范围内。

    Switched capacitor mixer circuit to attain high gain and linearity in radio frequency receivers
    8.
    发明授权
    Switched capacitor mixer circuit to attain high gain and linearity in radio frequency receivers 有权
    开关电容混频器电路，可在射频接收机中实现高增益和线性度

    公开(公告)号：US06957057B2

    公开(公告)日：2005-10-18

    申请号：US10123377

    申请日：2002-04-16

    Applicant: Mrinal Das

    Inventor： Mrinal Das

    IPC: H03D3/00 ,  H03D7/14 ,  H04B1/30 ,  H04B1/28 ,  H03B19/00

    CPC classification number: H04B1/30 ,  H03D3/008 ,  H03D7/1441 ,  H03D7/1491 ,  H03D2200/0025 ,  H03D2200/0084

    Abstract: By implementing the sampling process at an AC ground node, rather than at a signal side, and adding a gated transistor (610 and 620) in the signal path, the present invention reduces the interdependency between gain and linearity in a switched capacitor mixer circuit, supplies higher power without sacrificing area and simplifies the implementation of the RF switch. Charge boosting circuitry (630) allows a reduction in the effective size of a series switch (610 and 620) that follows a transconductance element (115).

    Abstract translation: 通过在交流接地节点而不是在信号侧实施采样过程，并且在信号路径中增加门控晶体管（610和620），本发明减小了开关电容器混频器电路中的增益和线性之间的相互依赖关系， 提供更高的功率而不牺牲区域，简化了RF开关的实现。 充电提升电路（630）允许减小跟随跨导元件（115）的串联开关（610和620）的有效尺寸。

    Silicon carbide devices with hybrid well regions
    10.
    发明申请
    Silicon carbide devices with hybrid well regions 有权
    具有混合井区的碳化硅器件

    公开(公告)号：US20060289874A1

    公开(公告)日：2006-12-28

    申请号：US11513473

    申请日：2006-08-31

    Applicant: Mrinal Das ,  Sei-Hyung Ryu

    Inventor： Mrinal Das ,  Sei-Hyung Ryu

    IPC: H01L31/0312 ,  H01L29/76

    CPC classification number: H01L29/7802 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  Y10S438/931

    Abstract: MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer, an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer and/or an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide well portion corresponding to a p-type channel region of the MOSFET.

    Abstract translation: 提供了MOS通道器件和制造具有混合通道的器件的方法。 示例性器件包括垂直功率MOSFET，其包括碳化硅的混合阱区域以及制造这种器件的方法。 混合阱区可以包括在p型碳化硅外延层中注入的p型碳化硅阱部分，注入的p型碳化硅接触部分，其与注入的p型碳化硅阱部分接触并延伸到表面 的p型外延层和/或外延p型碳化硅部分的至少一部分，所述外延p型碳化硅阱部分的至少一部分对应于所述MOSFET的p型沟道区。

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