公开(公告)号：US07532138B2

公开(公告)日：2009-05-12

申请号：US12035344

申请日：2008-02-21

申请人： Taiji Akizuki ,  Tomoaki Maeda ,  Masahiko Sagisaka

发明人： Taiji Akizuki ,  Tomoaki Maeda ,  Masahiko Sagisaka

IPC分类号： H03M3/00

CPC分类号： H03M3/394 ,  H03M3/422 ,  H03M3/454 ,  H03M7/3015 ,  H03M7/3024 ,  H03M7/304

摘要： In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.

摘要翻译： 在包括第一和第二减法器的Δ-Σ调制器中，第一和第二积分器，量化器和DA转换器，第一反馈电路包括第一电荷保持电路，其保持来自DA转换器的模拟信号的电荷用于不同的采样间隔， 可以改变来自DA转换器的模拟信号的反馈量，并将来自每个第一电荷保持电路的模拟信号输出到第二减法器。 第二反馈电路包括第二电荷保持电路，其保持来自第二积分器的模拟信号的电荷用于不同的采样间隔，可以改变来自第二积分器的模拟信号的反馈量，并且从第二电荷中的每一个输出模拟信号 保持电路到第二减法器。 控制器通过改变第一和第二反馈电路的反馈量来切换Δ-Σ调制器的滤波器特性的顺序。

公开(公告)号：US07321634B2

公开(公告)日：2008-01-22

申请号：US11015608

申请日：2004-12-17

申请人： Herbert L. Ko

发明人： Herbert L. Ko

IPC分类号： H04L27/00

CPC分类号： H03M7/3015

摘要： A method and apparatus for modulating a digital input signal is disclosed. The digital input signal is partitioned into a less-significant bit signal and a more-significant bit signal. A lower-order modulation of the less-significant bit signal is performed to generate an intermediate output signal. The intermediate output signal is appended to the more-significant bit signal to form an intermediate input signal. A higher-order modulation of the intermediate input signal is performed to generate a digital output signal. The higher-order modulation is of an order higher than the lower-order modulation. A phase-locked loop using the method and apparatus is disclosed.

摘要翻译： 公开了一种用于调制数字输入信号的方法和装置。 数字输入信号被划分为较低有效位信号和更高有效位信号。 执行较低有效位信号的低阶调制以产生中间输出信号。 中间输出信号附加到更高有效位信号以形成中间输入信号。 执行中间输入信号的高阶调制以产生数字输出信号。 高阶调制的次序比低阶调制高。 公开了使用该方法和装置的锁相环。

公开(公告)号：US07190288B2

公开(公告)日：2007-03-13

申请号：US10608932

申请日：2003-06-27

申请人： Ian Stuart Robinson ,  Jeffrey Mark Hinrichs ,  Jasmine Upendra Patel ,  Paul Charles MacFalda ,  Reza Dehmohseni ,  Frederic J. Harris ,  Kenneth Weber

发明人： Ian Stuart Robinson ,  Jeffrey Mark Hinrichs ,  Jasmine Upendra Patel ,  Paul Charles MacFalda ,  Reza Dehmohseni ,  Frederic J. Harris ,  Kenneth Weber

IPC分类号： H03M7/00

CPC分类号： H03M7/3015

摘要： Signal conversion is implemented employing a memory system operating as a look-up table that stores a plurality of sets of output samples associated with each of a plurality of respective input samples. The look-up table thus can generate a corresponding set of output samples in response to a given input sample, thereby emulating desired digital upsampling and delta-sigma modulation. The output samples can be aggregated, such as by multiplexing, to provide an output data stream at a desired sample rate.

摘要翻译： 使用作为查找表操作的存储器系统来实现信号转换，所述查找表存储与多个相应输入样本中的每一个相关联的多组输出采样。 因此，查找表可以响应于给定的输入采样产生相应的一组输出样本，从而仿真期望的数字上采样和Δ-Σ调制。 输出样本可以聚合，例如通过多路复用，以提供期望采样率的输出数据流。

公开(公告)号：US07130327B2

公开(公告)日：2006-10-31

申请号：US10608926

申请日：2003-06-27

申请人： Ian Stuart Robinson ,  Jeffrey Mark Hinrichs ,  Kenneth Weber

发明人： Ian Stuart Robinson ,  Jeffrey Mark Hinrichs ,  Kenneth Weber

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H03M7/3015 ,  G06F1/0321

摘要： Frequency synthesis is implemented by providing a delta-sigma modulated signal associated with a selected frequency, which frequency can vary based on a selection input. The delta-sigma modulated signal is converted from the digital to analog domain. The delta-sigma modulated signal can be provided directly from memory based on the selection input or, alternatively, it can be provided by a signal generator and processed by a delta-sigma modulator to provide the delta-sigma modulated signal. The selected frequency can be varied at a high rate of speed.

摘要翻译： 通过提供与所选频率相关联的Δ-Σ调制信号来实现频率合成，该频率可以基于选择输入而变化。 Δ-Σ调制信号从数字转换为模拟域。 Δ-Σ调制信号可以基于选择输入从存储器直接提供，或者可以由信号发生器提供并由Δ-Σ调制器处理以提供Δ-Σ调制信号。 所选择的频率可以以高速度变化。

公开(公告)号：US06943716B2

公开(公告)日：2005-09-13

申请号：US10731885

申请日：2003-12-08

申请人： Andrew Martin Mallinson

发明人： Andrew Martin Mallinson

IPC分类号： H03M3/02 ,  H03M1/30

CPC分类号： H03M7/3015 ,  H03M3/39 ,  H03M3/50 ,  H03M7/3028

摘要： A sigma delta circuit is provided having a sigma delta modulator configured to operate according to a first clock signal and a quantizer connected to the sigma delta modulator, where the quantizer is configured to operate according to a second clock signal. In operation, if a small amplitude signal is received by the sigma delta circuit, the circuit is configured to operate at a fixed output frequency. When a large amplitude signal is received, the circuit is configured to adjust to a different frequency to accommodate the larger signal. The second clock signal may be a variable clock signal, where the quantizer operates according to a variable clock signal in order to adjust to different input signals.

摘要翻译： 提供了一个Σ-Δ电路，其具有被配置为根据第一时钟信号和连接到Σ-Δ调制器的量化器进行操作的Σ-Δ调制器，其中量化器被配置为根据第二时钟信号进行操作。 在操作中，如果Σ-Δ电路接收到小振幅信号，则电路被配置为以固定的输出频率工作。 当接收到大振幅信号时，电路被配置成调节到不同的频率以适应较大的信号。 第二时钟信号可以是可变时钟信号，其中量化器根据可变时钟信号进行操作，以便调整到不同的输入信号。

公开(公告)号：US06839012B2

公开(公告)日：2005-01-04

申请号：US10635638

申请日：2003-08-07

申请人： Akinobu Kawamura

发明人： Akinobu Kawamura

IPC分类号： H03M3/02 ,  H03M7/32 ,  H03M3/00

CPC分类号： H03M7/3015 ,  H03M7/3022 ,  H03M7/3028 ,  H03M7/3037 ,  H03M7/304

摘要： The variable-order delta sigma modulator of the invention is capable of setting an optimum order in relation to a sampling frequency to be used, when using one out of plural sampling frequencies. As to the delta sigma modulator of the third order or higher, in a combination of two arbitrary continued integrators constituting the modulator is furnished a means that connects or disconnects the circuit on the second integrator side at the part of connecting the first integrator and the second integrator, or a means of switching the relation of connections. Connecting or disconnecting the circuit through the means and switching the relation of connections will set the order of the delta sigma modulator into an optimum order in relation to a sampling frequency.

公开(公告)号：US06804291B1

公开(公告)日：2004-10-12

申请号：US09510085

申请日：2000-02-22

申请人： Prakash Easwaran ,  Mrinal Das

发明人： Prakash Easwaran ,  Mrinal Das

IPC分类号： H04B138

CPC分类号： H03M7/3015 ,  H03M7/3026 ,  H03M7/304

摘要： A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.

公开(公告)号：US06795005B2

公开(公告)日：2004-09-21

申请号：US10453426

申请日：2003-06-03

申请人： James R. Hochschild

发明人： James R. Hochschild

IPC分类号： H03M300

CPC分类号： H03M7/3015

摘要： An improved sigma-delta modulation technique that may be employed in a sigma-delta Digital-to-Analog Converter (DAC) to convert digital signals into corresponding analog signals over a wide signal range and with high linearity. The sigma-delta DAC comprises a sigma-delta modulator including a variable quantizer and a quantizer controller, and an internal DAC. The sigma-delta modulator adaptively quantizes the digital input signal to a first number p of quantization levels. Next, the quantizer controller controls the variable quantizer to correlate the p quantization levels to the amplitude of the digital input signal, thereby generating a second number q of quantization levels. The internal DAC then receives the q quantization levels from the variable quantizer one group of p levels at a time, and produces an analog output signal therefrom that corresponds to the digital input signal.

摘要翻译： 可以在Σ-Δ数模转换器（DAC）中采用的改进的Σ-Δ调制技术，以将数字信号在宽信号范围内以高线性度转换成对应的模拟信号。 Σ-ΔDAC包括包括可变量化器和量化器控制器以及内部DAC的Σ-Δ调制器。 Σ-Δ调制器将数字输入信号自适应量化为第一数量级的量化级。 接下来，量化器控制器控制可变量化器以将p量化级与数字输入信号的幅度相关联，从而产生量化级的第二数量q。 然后，内部DAC一次从可变量化器一组p电平接收q量化电平，并从其产生对应于数字输入信号的模拟输出信号。

公开(公告)号：US20020126027A1

公开(公告)日：2002-09-12

申请号：US09757101

申请日：2001-01-08

发明人： Richard C. Walker

IPC分类号： H03M003/00

CPC分类号： H03M7/3015 ,  H03M7/3051

摘要： In accordance with one aspect of the invention, a method operates to compare an input value of the input signal stream with an output value of an integration function of a previous binary value to generate a new binary value based upon the comparison. The method then stores a plurality of successive binary values from the comparing step, and simulates an integration function for a plurality of possible bit sequences of the plurality of successive binary values. Finally, the method determines which sequence results in the smallest error between the input signal stream and the output value of the integration function, and uses the most significant bit of the determined sequence to adjust the integration function. In accordance with another aspect of the invention, an encoder is provided for encoding an input signal stream. The encoder includes a comparator configured to compare an input value of the input signal stream with an output value of an integration function of a previous binary value to generate a new binary value based upon the comparison. The encoder further includes a memory configured to store a plurality of successive binary values from the comparator, and means for simulating an integration function for a plurality of possible bit sequences of the plurality of successive binary values. The comparator further includes means for determining which sequence results in the smallest error between the input signal stream and the output value of the integration function, and means for adjusting the integration function based upon the most significant bit of the determined sequence.

摘要翻译： 根据本发明的一个方面，一种方法用于将输入信号流的输入值与先前二进制值的积分函数的输出值进行比较，以基于该比较生成新的二进制值。 该方法然后从比较步骤存储多个连续的二进制值，并且模拟多个连续二进制值中的多个可能位序列的积分函数。 最后，该方法确定哪个序列导致输入信号流与积分函数的输出值之间的最小误差，并使用确定序列的最高有效位来调整积分函数。 根据本发明的另一方面，提供了一种用于编码输入信号流的编码器。 编码器包括比较器，其被配置为将输入信号流的输入值与先前二进制值的积分函数的输出值进行比较，以基于该比较生成新的二进制值。 编码器还包括被配置为存储来自比较器的多个连续二进制值的存储器，以及用于模拟多个连续二进制值的多个可能位序列的积分函数的装置。 比较器还包括用于确定哪个序列导致输入信号流和积分函数的输出值之间的最小误差的装置，以及用于基于确定的序列的最高有效位来调整积分函数的装置。

公开(公告)号：US20170331491A1

公开(公告)日：2017-11-16

申请号：US15528164

申请日：2015-11-18

申请人： NEC Corporation

发明人： Masaaki TANIO ,  Shinichi HORI

IPC分类号： H03M7/30 ,  H04B14/06 ,  H03M3/02 ,  G06F7/60 ,  H03L7/197 ,  H03L7/081 ,  H03F3/24 ,  H04L27/36

CPC分类号： H03M7/304 ,  G06F7/602 ,  H03F3/2171 ,  H03F3/24 ,  H03F3/245 ,  H03L7/0816 ,  H03L7/1976 ,  H03M3/02 ,  H03M3/37 ,  H03M3/502 ,  H03M7/3011 ,  H03M7/3015 ,  H04B14/062 ,  H04L27/36

摘要： The purpose of the present invention is to provide a high-power-efficiency and low-design-cost transmission device by implementing, with a constant clock, delta-sigma modulation maintaining a zero current switching property in an amplifier. This delta-sigma modulator comprises: a pulse phase signal generation unit for generating a pulse phase signal from a phase signal; a delta-sigma modulation unit for generating a pulse amplitude signal obtained by delta-sigma modulating an amplitude signal with a constant clock; a phase sorting unit for outputting a control signal on the basis of the phase signal; a delay switching unit for delaying the pulse amplitude signal on the basis of the control signal; and a mixing unit for outputting a pulse string obtained by multiplying together the delayed pulse amplitude signal and the pulse phase signal.