公开(公告)号：US20110140743A1

公开(公告)日：2011-06-16

申请号：US12683137

申请日：2010-01-06

Applicant: Andrew Martin Mallinson

Inventor： Andrew Martin Mallinson

IPC: H03B21/00 ,  G06G7/16

CPC classification number: G06F1/025

Abstract: A digital frequency generator is described.

Abstract translation: 描述数字频率发生器。

公开(公告)号：US07028070B2

公开(公告)日：2006-04-11

申请号：US10057087

申请日：2002-01-26

Applicant: Andrew Martin Mallinson

Inventor： Andrew Martin Mallinson

IPC: G06G1/02

CPC classification number: H03H15/00 ,  G06G7/1928

Abstract: An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

公开(公告)号：US06646585B2

公开(公告)日：2003-11-11

申请号：US10118224

申请日：2002-04-05

Applicant: Andrew Martin Mallinson

Inventor： Andrew Martin Mallinson

IPC: H03M136

CPC classification number: H03M1/367

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract translation: 一种差分输入闪存模数转换器，其中连接比较器阵列以比较通过在阻抗网络上施加差分输入信号产生的这种信号的抛物面分布中的参考信号。 优选地，比较器阵列包括至少两个多个比较器，第一多个比较器比较由第一步长分隔的参考节点对，而第二多个比较器比较由第二步长分隔的参考节点对。 甚至更优选地，比较器阵列还包括第三多个比较器，其将由第三步长分隔的参考节点对进行比较，但仅在必要时使转换器的可用比较范围最大化。 根据本发明的闪存转换器从输入提供增加的增益，而不会累积比较器输入电流，并且不牺牲参考信号的实际比较的数量。

公开(公告)号：US20080005215A1

公开(公告)日：2008-01-03

申请号：US11479410

申请日：2006-06-30

Applicant: Andrew Martin Mallinson ,  Dustin Forman

Inventor： Andrew Martin Mallinson ,  Dustin Forman

IPC: G06F17/10

CPC classification number: H03F3/217 ,  H03F1/305

Abstract: The invention has been described in the context of a system and method of removing artifacts from an audio signal during shutdown of the output. The system includes a means by which the average value may be found to be zero or sufficiently close to zero as determined by the resolution of the filter output and a means by which the filter average value being zero or close to zero is used to disconnect (or equivalently change impedance or power) of the device or devices rendering the PWM signal into the analog domain as may be implemented by a Class D bridge chip and disconnection means.

Abstract translation: 已经在关于输出关闭期间从音频信号中去除伪影的系统和方法的上下文中描述了本发明。 该系统包括通过滤波器输出的分辨率确定的平均值可以被发现为零或足够接近零的装置，并且使用滤波器平均值为零或接近零的装置来断开（ 或等效地改变阻抗或功率），使得将PWM信号转换成可由D类桥芯片和断开装置实现的模拟域。

公开(公告)号：US06954165B2

公开(公告)日：2005-10-11

申请号：US10810310

申请日：2004-03-26

Applicant: Andrew Martin Mallinson

Inventor： Andrew Martin Mallinson

IPC: H03M20060101 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/66 ,  H03M1/68 ,  H03M1/76 ,  H03M1/78

CPC classification number: H03M1/0604 ,  H03M1/682 ,  H03M1/765

Abstract: An improved segmented digital to analog converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements. In further contrast to conventional devices, a second and third successive voltage segmenting elements, where a third segmented series of resistors has a third set of resistors connected end to end from along which an output can be generated at any point between the resistors, wherein the third segmented series of resistors further includes one current source connected at one end of the third series of resistors, and a second current source connected at another end of the third series of resistors.

Abstract translation: 提供了一种改进的分段数模转换器，其配置有补偿次级或连续分段元件中的电流的新颖方法。 在操作中，双电流装置最初加载，随后卸载连接到次级或连续电压分段元件的级联的电阻网络，以防止主要或先前元件的精确操作的扰动。 与常规方法相比，改进的转换器不需要缓冲器或放大器来隔离次级和连续的电压分段元件与初级元件或先前元件。 与传统器件相反，第二和第三连续的电压分段元件，其中第三分段串联的电阻器具有端到端连接的第三组电阻器，沿着该电阻器可以在电阻器之间的任何点产生输出，其中， 第三分段电阻器系列还包括连接在第三系列电阻器的一端的一个电流源和连接在第三系列电阻器的另一端的第二电流源。

公开(公告)号：US06897727B2

公开(公告)日：2005-05-24

申请号：US10680811

申请日：2003-10-06

Applicant: Andrew Martin Mallinson

Inventor： Andrew Martin Mallinson

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/45094 ,  H03F3/005 ,  H03F2203/45461

Abstract: A device is provided having at least two capacitive elements configured to retain a charge, and an interconnection of active devices between the capacitive elements. The active devices are configured to operate upon a transient charge flow as a current when in operation. The charge flow is partitioned into at least two capacitors according to the input voltage difference acting as a controlling parameter.

Abstract translation: 提供了一种器件，其具有被配置为保持电荷的至少两个电容元件以及在电容元件之间的有源器件的互连。 有源器件被配置为在瞬时充电流动时作为工作时的电流工作。 根据作为控制参数的输入电压差，将电荷流分成至少两个电容器。

公开(公告)号：US06803871B2

公开(公告)日：2004-10-12

申请号：US10346034

申请日：2003-01-15

Applicant: Andrew Martin Mallinson

Inventor： Andrew Martin Mallinson

IPC: H03M136

CPC classification number: H03M1/367

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract translation: 一种差分输入闪存模数转换器，其中连接比较器阵列以比较通过在阻抗网络上施加差分输入信号产生的这种信号的抛物面分布中的参考信号。 优选地，比较器阵列包括至少两个多个比较器，第一多个比较器比较由第一步长分隔的参考节点对，而第二多个比较器比较由第二步长分隔的参考节点对。 甚至更优选地，比较器阵列还包括第三多个比较器，其将由第三步长分隔的参考节点对进行比较，但仅在必要时使转换器的可用比较范围最大化。 根据本发明的闪存转换器从输入提供增加的增益，而不会累积比较器输入电流，并且不牺牲参考信号的实际比较的数量。

公开(公告)号：US07902877B1

公开(公告)日：2011-03-08

申请号：US12683182

申请日：2010-01-06

Applicant: Dustin D. Forman ,  Andrew Martin Mallinson

Inventor： Dustin D. Forman ,  Andrew Martin Mallinson

IPC: H03K19/00

CPC classification number: H03B27/00 ,  G11C19/00 ,  G11C19/28 ,  G11C27/024

Abstract: A multiphase clock generates pulses at a rate much higher than the clock frequency.

Abstract translation: 多相时钟以比时钟频率高得多的速率产生脉冲。

公开(公告)号：US07680173B2

公开(公告)日：2010-03-16

申请号：US11479537

申请日：2006-06-30

Applicant: Andrew Martin Mallinson ,  Simon Damphousse

Inventor： Andrew Martin Mallinson ,  Simon Damphousse

IPC: H04B1/69

CPC classification number: H04B15/02 ,  H04B1/707 ,  H04B2215/067

Abstract: A system and method are provided for performing a spread spectrum clock generation, where the system includes self-adjusting delay line configured to spread the spectrum of a fixed circuit using a fixed clock frequency and a delay circuit configured to generate an adjustment signal to the delay line by adding or subtracting an addition delay per cycle, therefore causing a shift in the output clock frequency, wherein the amount of shift is proportional to the rate of addition or subtraction of delay.

Abstract translation: 提供了一种用于执行扩频时钟生成的系统和方法，其中系统包括自适应延迟线，其被配置为使用固定时钟频率来扩展固定电路的频谱，并且延迟电路被配置为产生到延迟的调整信号 通过增加或减去每个周期的相加延迟，因此引起输出时钟频率的偏移，其中移位量与延迟的相加或减法的比例成比例。

公开(公告)号：US07457836B2

公开(公告)日：2008-11-25

申请号：US11691412

申请日：2007-03-26

Applicant: Andrew Martin Mallinson

Inventor： Andrew Martin Mallinson

IPC: G06F7/68

CPC classification number: H03M7/3004 ,  H03H17/0248 ,  H03M7/3028 ,  H03M7/3042

Abstract: The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.

Abstract translation: 本发明涉及一种双向滤波器电路，其配置为以二进制比率乘法器（BRM）操作的Σ-Δ器件。 与传统的双通道滤波器电路不同，本发明提供一种配置有单位BRM的双通道滤波器。 在另一个实施例中，本发明还提供一种配置有多位BRM的双二进制滤波器。