公开(公告)号：US06720902B2

公开(公告)日：2004-04-13

申请号：US10163733

申请日：2002-06-06

申请人： Eric Stimmann

发明人： Eric Stimmann

IPC分类号： H03M136

CPC分类号： H03M1/187

摘要： The present invention provides a single analog-to-digital converter system which is capable of converting an input signal having a high dynamic range into a digital signal which is within the range of the analog-to-digital converter. Additionally, the present invention provides an analog-to-digital converter which is capable of converting an input signal having a high dynamic range into a digital signal by controlling the amplification of the signal to achieve the optimal gain that falls within the range of the analog-to-digital converter.

摘要翻译： 本发明提供了一种能够将具有高动态范围的输入信号转换成模数转换器范围内的数字信号的单个模 - 数转换器系统。 此外，本发明提供了一种模数转换器，其能够通过控制信号的放大来将具有高动态范围的输入信号转换为数字信号，以实现落在模拟信号范围内的最佳增益 数字转换器。

公开(公告)号：US06707413B2

公开(公告)日：2004-03-16

申请号：US10234596

申请日：2002-09-04

申请人： Koji Sushihara ,  Akira Matsuzawa

发明人： Koji Sushihara ,  Akira Matsuzawa

IPC分类号： H03M136

CPC分类号： H03M1/204 ,  H03M1/365

摘要： An A/D converter of the present invention includes: a reference voltage generation section for generating a plurality of reference voltages; a differential amplification section for amplifying a voltage difference between each of the plurality of reference voltages and an input signal voltage so as to generate a plurality of output voltage sets, each of the plurality of output voltage sets including complementary non-inverted and inverted output voltages; and an operating section for receiving the plurality of output voltage sets, the operating section being operated according to a clock signal.

摘要翻译： 本发明的A / D转换器包括：用于产生多个参考电压的参考电压产生部分; 差分放大部分，用于放大多个参考电压中的每个参考电压和输入信号电压之间的电压差，以产生多个输出电压组，所述多个输出电压组中的每一个包括互补的非反相和反相输出电压 ; 以及用于接收多个输出电压组的操作部分，所述操作部分根据时钟信号进行操作。

公开(公告)号：US06437724B1

公开(公告)日：2002-08-20

申请号：US09662274

申请日：2000-09-14

申请人： Krishnaswamy Nagaraj

发明人： Krishnaswamy Nagaraj

IPC分类号： H03M136

CPC分类号： H03M1/0682 ,  H03M1/363

摘要： An electronic circuit for converting an analog differential signal into a corresponding digital signal includes 2n voltage comparators each having a first input terminal, a second input terminal and an output terminal. A first network of 2n resistive elements is provided to which a first analog signal of the differential signal is applied, the first network having a plurality of first network nodes each coupled to the first input terminal of a corresponding one of the comparators and wherein one of the first network nodes is a first middle node coupled to the first analog signal. A second network of 2n resistive elements is provided to which a second analog signal of the differential signal is applied, the second network having a plurality of second network nodes each coupled to the second input terminal of the corresponding one of the comparators and wherein one of the second network nodes is a second middle node coupled to the second analog signal. The disclosed circuit couples a differential input signal to the capacitor array without the need for capacitors. This simplifies implementation and saves power and area. Such analog-to-digital converters are vital for high speed data communication and storage application.

摘要翻译： 用于将模拟差分信号转换为对应的数字信号的电子电路包括2n个电压比较器，每个电压比较器具有第一输入端，第二输入端和输出端。 提供2n个电阻元件的第一网络，其上施加差分信号的第一模拟信号，第一网络具有多个第一网络节点，每个第一网络节点耦合到对应的一个比较器的第一输入端子，并且其中， 第一网络节点是耦合到第一模拟信号的第一中间节点。 提供2n个电阻元件的第二网络，其上施加差分信号的第二模拟信号，第二网络具有多个第二网络节点，每个第二网络节点耦合到对应的一个比较器的第二输入端子，并且其中， 第二网络节点是耦合到第二模拟信号的第二中间节点。 所公开的电路将差分输入信号耦合到电容器阵列而不需要电容器。 这简化了实现并节省了功率和面积。 这种模数转换器对于高速数据通信和存储应用至关重要。

公开(公告)号：US06369732B1

公开(公告)日：2002-04-09

申请号：US09726331

申请日：2000-12-01

申请人： Hung-Chih Liu ,  Wei-Chen Shen

发明人： Hung-Chih Liu ,  Wei-Chen Shen

IPC分类号： H03M136

CPC分类号： H03M1/36 ,  H03M1/0646 ,  H03M1/0682

摘要： The present invention is to provide a low voltage fully differential analog-to-digital converter. The converter consists of an input stage including a plurality of pre-amplifier differential input cells for producing pre-amplified signals, a successive processing stage for receiving pre-amplified signals from the input stages, and a decoder for output converted signals according to the signals from the successive processing stage. Each differential input cell includes first and second differential pre-amplifiers, a bias impedance, and an averaging impedance branch. The first and second differential pre-amplifiers include two transistors, respectively, and differentially amplify a set of input signals. One terminal of the bias impedance is connected to a high supplied voltage while the other terminal of the bias impedance is connected to the first and second output terminals through respective pieces of load bearing impedance in order to adjust output voltages of first and second output terminals. Moreover, the averaging impedance branch includes an impedance connecting the second output terminal and the first output terminal of an adjacent differential input cell and another impedance connecting the other end of the bias impedance and the other end of the bias impedance of the adjacent differential input cell.

摘要翻译： 本发明是提供一种低电压全差分模拟 - 数字转换器。 该转换器包括一个输入级，该输入级包括用于产生预放大信号的多个前置放大器差分输入单元，用于接收来自输入级的预放大信号的连续处理级，以及根据该信号输出转换信号的解码器 从连续的处理阶段。 每个差分输入单元包括第一和第二差分前置放大器，偏置阻抗和平均阻抗分支。 第一和第二差分前置放大器分别包括两个晶体管，差分放大一组输入信号。 偏置阻抗的一个端子连接到高供电电压，而偏置阻抗的另一个端子通过相应的承载阻抗件连接到第一和第二输出端子，以便调节第一和第二输出端子的输出电压。 此外，平均阻抗分支包括连接相邻差分输入单元的第二输出端子和第一输出端子的阻抗，以及连接偏置阻抗的另一端和相邻差分输入单元的偏置阻抗的另一端的另一阻抗 。

公开(公告)号：US06288666B1

公开(公告)日：2001-09-11

申请号：US09436073

申请日：1999-11-08

申请人： Morteza Afghahi ,  Yueming He

发明人： Morteza Afghahi ,  Yueming He

IPC分类号： H03M136

CPC分类号： H03K5/2481 ,  H03K5/249

摘要： An embodiment of the invention is directed to a metal oxide semiconductor field effect transistor (MOSFET) comparator, which includes a differential amplifier having first and second inputs and first and second outputs. A first offset storage device is connected to the first input at one end and receives a first input signal of the comparator at another end. A second offset storage device is connected to the second input at one end and receives the first input signal during an autozero time interval and a second input signal of the comparator thereafter. During the autozero time interval, offset voltages are stored. Thereafter, the offsets are cancelled when the input signals are applied to their respective storage device. In a particular embodiment of the invention, the amplifier features a dual purpose load that causes the amplifier to first preamplify and then regeneratively drives the outputs.

摘要翻译： 本发明的实施例涉及一种金属氧化物半导体场效应晶体管（MOSFET）比较器，其包括具有第一和第二输入以及第一和第二输出的差分放大器。 第一偏移存储装置在一端连接到第一输入端，并在另一端接收比较器的第一输入信号。 第二偏移存储装置在一端连接到第二输入端，并且在自动零时间间隔期间接收第一输入信号，然后在比较器之后接收比较器的第二输入信号。 在自动调零时间间隔内，存储偏移电压。 此后，当输入信号被施加到它们各自的存储装置时，抵消偏移。 在本发明的特定实施例中，放大器具有双用途负载，其使得放大器首先对其进行预放大，然后再生驱动输出。

公开(公告)号：US06232907B1

公开(公告)日：2001-05-15

申请号：US09315246

申请日：1999-05-20

申请人： Krishnaswamy Nagaraj ,  T. R. Viswanathan

发明人： Krishnaswamy Nagaraj ,  T. R. Viswanathan

IPC分类号： H03M136

CPC分类号： H03M1/361

摘要： An A/D converter which includes a sample-and-hold circuit having an input and an output, a zero-crossing detector having an input coupled to the output of the sample-and-hold circuit and having an output indicative of a change in polarity of an input signal thereto and a polarity reverser having an input coupled to the output of the sample-and-hold circuit, a control terminal coupled to and under control of the output of the zero-crossing detector and an output terminal. A bank of comparators, preferably in a first and second array, each have inputs respectively coupled to the output of the polarity reverser, each comparator having an output. An encoder preferably having first and second portions is coupled to the output of the comparator, the first array preferably coupled to the first encoder portion and the second array preferably coupled to the second encoder portion, the encoder having an output. A multiplexer is optionally coupled to the first and second encoder portions and responsive to a predetermined signal from the second encoder portion to select signals from the outputs of one of the first and second encoders. A pair of buffers are optionally provided, a first buffer coupled between the output of the sample-and-hold circuit and both the polarity reverser and the zero crossing detector and a second buffer coupled between the output of the sample-and-hold circuit and the second array of comparators. First and second switches are optionally provided, the first switches being operational only during a first repeating time window for coupling the first buffer to the zero crossing detector and the polarity reverser and coupling the second buffer to the second array of comparators and the second switches are operational only during a second repeating time window not overlapping the first time window for coupling said second buffer to said zero crossing detector and said polarity reverser.

摘要翻译： 一种A / D转换器，其包括具有输入和输出的采样和保持电路，过零检测器，具有耦合到采样保持电路的输出的输入端，并具有指示变化的输出 输入信号的极性和具有耦合到采样保持电路的输出的输入的极性反转器，耦合到过零检测器的输出端和输出端子的控制端子。 优选地具有第一和第二阵列的比较器组各自具有分别耦合到极性反相器的输出的输入，每个比较器具有输出。 优选地具有第一和第二部分的编码器耦合到比较器的输出端，第一阵列优选地耦合到第一编码器部分，而第二阵列优选地耦合到第二编码器部分，编码器具有输出。 复用器可选地耦合到第一和第二编码器部分，并且响应于来自第二编码器部分的预定信号来选择来自第一和第二编码器之一的输出的信号。 可选地提供一对缓冲器，第一缓冲器耦合在采样保持电路的输出端与极性反相器和过零检测器两者之间，第二缓冲器耦合在采样保持电路的输出和 第二组比较器。 可选地提供第一和第二开关，第一开关仅在第一重复时间窗口期间操作，用于将第一缓冲器耦合到过零检测器和极性反相器，并将第二缓冲器耦合到第二比较器阵列，并且第二开关 仅在与第一时间窗口不重叠的第二重复时间窗口中操作，用于将所述第二缓冲器耦合到所述过零检测器和所述极性反转器。

公开(公告)号：US06198421B1

公开(公告)日：2001-03-06

申请号：US09259650

申请日：1999-02-26

申请人： James T. Doyle ,  Carl F. Liepold

发明人： James T. Doyle ,  Carl F. Liepold

IPC分类号： H03M136

CPC分类号： H03M1/36

摘要： One embodiment of the present invention provides a flash analog-to-digital converter (ADC) based on a feedforward perceptron. The ADC includes a plurality of N stages to provide N digital signals. The plurality of N stages includes a first stage to provide a sum of an input current, related to a voltage to be converted, and of a reference current. The first stage provides a first digital signal in one of first and second states if the sum has one of first and second signs, respectively. The plurality of N stages further includes i stages, with i=2 . . . N. Each stage i includes an output circuit and 2(i−2) sub-stages coupled to the output circuit. Each sub-stage includes an input and a hidden circuit coupled therebetween. The input circuit is configured to provide a first sum of the input current and of a first reference current. Each hidden circuit provides to the output circuit a second reference current when the first sum has a first sign. The output circuit generates an ith digital signal in one of a first and second states when a second sum of the input current and of the second reference current has one of first and second signs respectively.

摘要翻译： 本发明的一个实施例提供一种基于前馈感知器的闪存模数转换器（ADC）。 ADC包括多个N级以提供N个数字信号。 多个N级包括提供与要转换的电压相关的输入电流和参考电流的和的第一级。 如果总和分别具有第一和第二符号之一，则第一级提供第一和第二状态之一的第一数字信号。 多个N级还包括i级，i = 2。 。 。 N.每级i包括一个输出电路和耦合到输出电路的2（i-2）个子级。 每个子级包括耦合在其间的输入和隐藏电路。 输入电路被配置为提供输入电流和第一参考电流的第一和。 当第一和具有第一符号时，每个隐藏电路向输出电路提供第二参考电流。 当输入电流和第二参考电流的第二和分别具有第一和第二符号之一时，输出电路产生第一和第二状态之一的第i个数字信号。

公开(公告)号：US06195031B1

公开(公告)日：2001-02-27

申请号：US09221048

申请日：1998-12-28

申请人： Peter Feld ,  Horst Kroeckel ,  Markus Vester

发明人： Peter Feld ,  Horst Kroeckel ,  Markus Vester

IPC分类号： H03M136

CPC分类号： H03M1/188

摘要： An analog-to-digital converter circuit for digitalizing a high-frequency signal with large dynamics has a first analog-to-digital converter and a second analog-to-digital converter connected in parallel, a level converter connected to one of the two analog-to-digital converters, a level recognition element for determining a level range in which the high-frequency signal lies and for generating a control signal dependent on the level range, and a correction memory that is connected to the level recognition element, the correction memory having address inputs connected to outputs of the analog-to-digital converters. The control signal is used as a selection criterion which identifies which analog-to-digital converter address data are taken from for producing a digital output signal, the digital output signal being linearized according to a characteristic of the selected analog-to-digital converter in order to correct for distortion arising in the selected converter. The overall analog-to-digital converter circuit thus has an overall linear characteristic, even as the input signal varies between low and high amplitudes.

摘要翻译： 用于以大动态数字化高频信号的模数转换器电路具有并联连接的第一模数转换器和第二模数转换器，电平转换器连接到两个模拟 数字转换器，用于确定高频信号所在的电平范围并用于产生取决于电平范围的控制信号的电平识别元件，以及连接到电平识别元件的校正存储器，校正 具有连接到模数转换器的输出的地址输入的存储器。 该控制信号用作选择标准，其标识从哪个模拟 - 数字转换器地址数据获取用于产生数字输出信号，数字输出信号根据所选择的模数转换器的特性被线性化 以纠正所选转换器中出现的失真。 因此，总体模数转换器电路具有总体线性特性，即使输入信号在低和高幅度之间变化。

公开(公告)号：US06803872B2

公开(公告)日：2004-10-12

申请号：US10143413

申请日：2002-05-09

申请人： John F. DeRyckere ,  Philip Nord Jenkins ,  Frank Nolan Cornett

发明人： John F. DeRyckere ,  Philip Nord Jenkins ,  Frank Nolan Cornett

IPC分类号： H03M136

CPC分类号： H03K5/135 ,  H03K2005/00208

摘要： Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

摘要翻译： 对早期到达信号提供附加延迟的电路，使得所有数据信号到达具有相同路径延迟的接收锁存器。 还控制转发的时钟参考的延迟，使得捕获时钟边缘将被最佳地定位在正交附近（取决于锁存器设置/保持要求）。 该电路连续适应数据和时钟路径延迟变化，并且相位测量的数字滤波可以减少抖动数据沿引起的误差。 电路仅利用实现目标所需的最小延迟量，从而限制任何非预期的抖动。 特别地，具有精细延迟调整的可编程差分延迟电路被设计为允许ASICS之间的偏斜最小化。 这包括数据位之间，数据位和时钟之间的偏差以及最小化ASICS之间通道中的总体偏移。

公开(公告)号：US06771203B1

公开(公告)日：2004-08-03

申请号：US10426648

申请日：2003-04-29

申请人： David Graham Nairn

发明人： David Graham Nairn

IPC分类号： H03M136

CPC分类号： H03M1/066 ,  H03M1/1215

摘要： Parallel analog-to-digital converter systems are provided in which converters are temporally interleaved. In particular, converters are partitioned into at least two converter groups which are assigned different respective group converter periods that are multiples of the system periods. With converters in each of the converter groups, respective samples are processed over that group's respective group converter period and the group converter periods of all converters are temporally shifted to process each of the samples with at least one of the converters. System spurious signals are thus reduced and, in another system embodiment, the reduced spurious lines are converted into the system's noise level by detecting instances when available converters that belong to different converter groups are available to process an upcoming one of the samples and, in at least a chosen one of the instances, exchanging the available converters between their different converter groups to thereby alter which processes the upcoming sample and which processes a subsequent sample. All converters continue to process respective samples.

摘要翻译： 提供并行模数转换器系统，其中转换器在时间上交错。 特别地，转换器被划分为至少两个转换器组，其被分配为系统周期的倍数的不同的相应组转换器周期。 利用每个转换器组中的转换器，通过该组相应的组转换器周期处理相应的采样，并且所有转换器的组转换器周期被时间偏移以用至少一个转换器来处理每个采样。 因此系统寄生信号被减少，并且在另一系统实施例中，通过检测属于不同转换器组的可用转换器可用于处理即将到来的一个采样的实例，通过检测实例，将降低的杂散线转换成系统的噪声电平，并且在 至少选择一个实例中，在其不同的转换器组之间交换可用的转换器，从而改变即将到来的样本的哪些处理以及后续样本的处理。 所有转换器继续处理各自的样品。