公开(公告)号：US07180933B2

公开(公告)日：2007-02-20

申请号：US10327271

申请日：2002-12-20

申请人： Ching-Lin Wu ,  Hsien-Feng Liu ,  Hung-Chih Liu

发明人： Ching-Lin Wu ,  Hsien-Feng Liu ,  Hung-Chih Liu

IPC分类号： H04L25/00

CPC分类号： H03G3/344 ,  H03G3/345

摘要： A squelch circuit for operating at high speed and at high frequencies includes a squelch input unit, a low swing pre-amplifier and a sampling and decision circuit. The squelch input unit pre-processes the positive and negative signals of an input signal to generate four pre-processed signals that are paired and sent to the low swing pre-amplifier. The outputs of the low-swing pre-amplifier are then over-sampled by the sampling and decision circuit. Multi-phase clocks are used to control the over-sampling in the sampling and decision circuit. A logic circuit then determines if the state of the input signal based on multiple samples.

摘要翻译： 用于高速和高频操作的静噪电路包括静噪输入单元，低摆幅前置放大器以及采样和判定电路。 静噪输入单元对输入信号的正和负信号进行预处理，以产生配对并发送到低摆幅前置放大器的四个预处理信号。 低摆幅前置放大器的输出由采样和判定电路过采样。 多相时钟用于控制采样和判定电路中的过采样。 然后，逻辑电路基于多个采样来确定输入信号的状态。

公开(公告)号：US06822601B1

公开(公告)日：2004-11-23

申请号：US10604458

申请日：2003-07-23

申请人： Hung-Chih Liu ,  Jieh-Tsomg Wu ,  Zwei-Mei Lee

发明人： Hung-Chih Liu ,  Jieh-Tsomg Wu ,  Zwei-Mei Lee

IPC分类号： H03M138

CPC分类号： H03M1/1004 ,  H03M1/167

摘要： A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.

摘要翻译： 倍增的数模转换器（MDAC）级包括多个并联的第二电容，其选择性地连接在输入节点和放大器输入之间以及相应的多个数字参考信号之间，所述数字参考信号可以包括伪随机的第一校准信号 ，和放大器输入。 包含一系列这样的MDAC级的流水线ADC包括连接到该系列的最后MDAC级的乘法器，用于滤波乘法器的输出和输出DC分量的低通滤波器以及用于接收MDAC级的输出的编码器 并产生数字输出信号并用DC补偿数字输出信号。 ADC的背景校准包括在保持阶段将第一校准信号施加到MDAC级的第二电容，以及从流水线模数转换器的数字输出滤波第一校准信号。

公开(公告)号：US06492871B2

公开(公告)日：2002-12-10

申请号：US09751981

申请日：2000-12-29

申请人： Hung-Chih Liu ,  Stanley Liao

发明人： Hung-Chih Liu ,  Stanley Liao

IPC分类号： H03F345

CPC分类号： H03F3/45659 ,  H03F3/45273

摘要： The present invention discloses a current feedback operational amplifier, whose input ends are connected to a first amplifier which transmits an output to the gate terminals of at least one input pair of current switches, and the source terminal of one transistor of the input pair of current switches is connected to one of the input ends. Therefore, a negative feedback loop will be established by the first amplifier and the input pair of current switches. By means of the negative feedback loop, the input impedance, offset voltage and gain error are all reduced. The input impedance of the present invention is reduced as 1/1+A times as the original one. Therefore, the aspect ratio of the transistors of the input pair of current switches is reduced.

摘要翻译： 本发明公开了一种电流反馈运算放大器，其输入端连接到第一放大器，该第一放大器向至少一个输入电流开关对的栅极端子发送输出，并且输入一对电流的一个晶体管的源极端子 开关连接到其中一个输入端。 因此，负反馈回路将由第一放大器和电流开关的输入对建立。 通过负反馈回路，输入阻抗，失调电压和增益误差均降低。 本发明的输入阻抗减少为原来的1/1 + A倍。 因此，输入一对电流开关的晶体管的纵横比减小。

公开(公告)号：US06650146B2

公开(公告)日：2003-11-18

申请号：US10006295

申请日：2001-12-06

申请人： Yin-shang Liu ,  Kuo-sheng Huang ,  Hung-chih Liu

发明人： Yin-shang Liu ,  Kuo-sheng Huang ,  Hung-chih Liu

IPC分类号： H03D1300

CPC分类号： H04L7/033 ,  H03D13/004 ,  H03L7/0891 ,  H03L7/091

摘要： A digital frequency comparator includes two double-edge triggered flip-flops and a combination logic. Each of the double-edge triggered flip-flops includes two D-type flip-flops and two multiplexers. The first D-type flip-flop receives a first reference clock pulse and is triggered by a data signal. The second D-type flip-flop receives the first reference clock pulse and is triggered by the reverse of the data signal. The first multiplexer provides the output of the first D-type flip-flop when the data signal is 1 and the output of the second D-type flip-flop when the data signal is 0. The second multiplexer provides the output of the first D-type flip-flop when the data signal is 0 and the output of the second D-type flip-flop when the data signal is 1. The combination logic enables an UP pulse when the data signal transmission clock is faster in frequency than the first reference clock signal.

摘要翻译： 数字频率比较器包括两个双边沿触发的触发器和组合逻辑。 每个双边沿触发的触发器包括两个D型触发器和两个多路复用器。 第一D型触发器接收第一参考时钟脉冲并由数据信号触发。 第二个D型触发器接收第一个参考时钟脉冲，并由数据信号的相反触发。 当数据信号为1时，第一个多路复用器提供第一个D型触发器的输出，当数据信号为0时，第二个多路复用器提供第二个D型触发器的输出。第二个多路复用器提供第一个D型触发器的输出 数据信号为0时的第二D型触发器的输出和数据信号为1时的第二D型触发器的输出。当数据信号传输时钟的频率比第一 参考时钟信号。

公开(公告)号：US06369732B1

公开(公告)日：2002-04-09

申请号：US09726331

申请日：2000-12-01

申请人： Hung-Chih Liu ,  Wei-Chen Shen

发明人： Hung-Chih Liu ,  Wei-Chen Shen

IPC分类号： H03M136

CPC分类号： H03M1/36 ,  H03M1/0646 ,  H03M1/0682

摘要： The present invention is to provide a low voltage fully differential analog-to-digital converter. The converter consists of an input stage including a plurality of pre-amplifier differential input cells for producing pre-amplified signals, a successive processing stage for receiving pre-amplified signals from the input stages, and a decoder for output converted signals according to the signals from the successive processing stage. Each differential input cell includes first and second differential pre-amplifiers, a bias impedance, and an averaging impedance branch. The first and second differential pre-amplifiers include two transistors, respectively, and differentially amplify a set of input signals. One terminal of the bias impedance is connected to a high supplied voltage while the other terminal of the bias impedance is connected to the first and second output terminals through respective pieces of load bearing impedance in order to adjust output voltages of first and second output terminals. Moreover, the averaging impedance branch includes an impedance connecting the second output terminal and the first output terminal of an adjacent differential input cell and another impedance connecting the other end of the bias impedance and the other end of the bias impedance of the adjacent differential input cell.

摘要翻译： 本发明是提供一种低电压全差分模拟 - 数字转换器。 该转换器包括一个输入级，该输入级包括用于产生预放大信号的多个前置放大器差分输入单元，用于接收来自输入级的预放大信号的连续处理级，以及根据该信号输出转换信号的解码器 从连续的处理阶段。 每个差分输入单元包括第一和第二差分前置放大器，偏置阻抗和平均阻抗分支。 第一和第二差分前置放大器分别包括两个晶体管，差分放大一组输入信号。 偏置阻抗的一个端子连接到高供电电压，而偏置阻抗的另一个端子通过相应的承载阻抗件连接到第一和第二输出端子，以便调节第一和第二输出端子的输出电压。 此外，平均阻抗分支包括连接相邻差分输入单元的第二输出端子和第一输出端子的阻抗，以及连接偏置阻抗的另一端和相邻差分输入单元的偏置阻抗的另一端的另一阻抗 。

公开(公告)号：US06624775B1

公开(公告)日：2003-09-23

申请号：US10175898

申请日：2002-06-21

申请人： Sheng-Yeh Lai ,  Hung-Chih Liu

发明人： Sheng-Yeh Lai ,  Hung-Chih Liu

IPC分类号： H03M166

CPC分类号： H03K17/04106

摘要： A current output circuit for use in a digital-to-analog converter is disclosed. The current output circuit includes a current source for providing a driving current, and a first output circuit coupled with the current source. The first output circuit includes a first metal-oxide semiconductor (MOS) transistor device having a source electrode thereof connected to the current source in series, a first voltage amplifier coupled between the source electrode and a gate electrode of the first MOS transistor device for keeping a voltage of the source electrode substantially constant, and a first controlled switch coupled between an operational voltage and the gate electrode of the first MOS transistor device for being switched ON or OFF in response to a first digital control signal, and allowing the driving current to be outputted from a drain electrode of the MOS transistor device when the first controlled switch is switched ON.

摘要翻译： 公开了一种用于数模转换器的电流输出电路。 电流输出电路包括用于提供驱动电流的电流源和与电流源耦合的第一输出电路。 第一输出电路包括其源电极串联连接到电流源的第一金属氧化物半导体（MOS）晶体管器件，耦合在源电极和第一MOS晶体管器件的栅电极之间的第一电压放大器，用于保持 源电极的电压基本恒定，以及耦合在第一MOS晶体管器件的工作电压和栅电极之间的第一受控开关，用于响应于第一数字控制信号被接通或断开，并且允许驱动电流 当第一受控开关接通时，从MOS晶体管器件的漏电极输出。

公开(公告)号：US06407630B1

公开(公告)日：2002-06-18

申请号：US09754168

申请日：2001-01-04

申请人： Chi-Tai Yao ,  Wei-Chen Shen ,  Hung-Chih Liu

发明人： Chi-Tai Yao ,  Wei-Chen Shen ,  Hung-Chih Liu

IPC分类号： H03F102

CPC分类号： H03F3/45659 ,  H03F3/45188

摘要： The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

摘要翻译： 本发明公开了一种应用在可变增益放大器中的DC偏移消除电路。 DC偏移消除电路包括跨导放大器和用作滤波器的至少一个内部电容器。 跨导放大器的输入电连接到可变增益放大器的输出，并且跨导放大器和至少一个内部电容器的输出电连接到可变增益放大器的输入端以形成反馈回路。 为了配合DC偏移消除的功能，可变增益放大器的输入级包括辅助差分对。

公开(公告)号：US06400199B1

公开(公告)日：2002-06-04

申请号：US09835798

申请日：2001-04-16

申请人： Hung-Chih Liu ,  Hsian-Feng Liu

发明人： Hung-Chih Liu ,  Hsian-Feng Liu

IPC分类号： H03K3289

CPC分类号： H03K3/35625 ,  H03K3/356139 ,  H03K17/693

摘要： A fully differential double edge triggered flip-flop stores and outputs first and second fully differential input values on leading and trailing edges of a clock. The flip-flop includes a first fully differential master circuit, a second fully differential master circuit and a fully differential slave circuit. The first master circuit stores the first input value during the period from the leading edge to trailing edge of the clock. The second master circuit stores the second input value during the period from the trailing edge to leading edge of the clock. The slave circuit is electrically connected to outputs of the first and second master circuits. The slave circuit includes a second repeater as an output end of the flip-flop, outputs the first input value on the trailing edge of the clock, and outputs the second input value on the leading edge of the clock.

摘要翻译： 全差分双边沿触发触发器在时钟的前沿和后沿存储并输出第一和第二全差分输入值。 触发器包括第一全差分主电路，第二全差分主电路和全差分从动电路。 第一主电路在从时钟的前沿到后沿的时段期间存储第一输入值。 第二主电路在从时钟的后沿到前沿的时段期间存储第二输入值。 从电路电连接到第一和第二主电路的输出。 从电路包括作为触发器的输出端的第二中继器，在时钟的后沿输出第一输入值，并在时钟的前沿输出第二输入值。