公开(公告)号：US06822601B1

公开(公告)日：2004-11-23

申请号：US10604458

申请日：2003-07-23

申请人： Hung-Chih Liu ,  Jieh-Tsomg Wu ,  Zwei-Mei Lee

发明人： Hung-Chih Liu ,  Jieh-Tsomg Wu ,  Zwei-Mei Lee

IPC分类号： H03M138

CPC分类号： H03M1/1004 ,  H03M1/167

摘要： A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.

摘要翻译： 倍增的数模转换器（MDAC）级包括多个并联的第二电容，其选择性地连接在输入节点和放大器输入之间以及相应的多个数字参考信号之间，所述数字参考信号可以包括伪随机的第一校准信号 ，和放大器输入。 包含一系列这样的MDAC级的流水线ADC包括连接到该系列的最后MDAC级的乘法器，用于滤波乘法器的输出和输出DC分量的低通滤波器以及用于接收MDAC级的输出的编码器 并产生数字输出信号并用DC补偿数字输出信号。 ADC的背景校准包括在保持阶段将第一校准信号施加到MDAC级的第二电容，以及从流水线模数转换器的数字输出滤波第一校准信号。