公开(公告)号：US06232907B1

公开(公告)日：2001-05-15

申请号：US09315246

申请日：1999-05-20

申请人： Krishnaswamy Nagaraj ,  T. R. Viswanathan

发明人： Krishnaswamy Nagaraj ,  T. R. Viswanathan

IPC分类号： H03M136

CPC分类号： H03M1/361

摘要： An A/D converter which includes a sample-and-hold circuit having an input and an output, a zero-crossing detector having an input coupled to the output of the sample-and-hold circuit and having an output indicative of a change in polarity of an input signal thereto and a polarity reverser having an input coupled to the output of the sample-and-hold circuit, a control terminal coupled to and under control of the output of the zero-crossing detector and an output terminal. A bank of comparators, preferably in a first and second array, each have inputs respectively coupled to the output of the polarity reverser, each comparator having an output. An encoder preferably having first and second portions is coupled to the output of the comparator, the first array preferably coupled to the first encoder portion and the second array preferably coupled to the second encoder portion, the encoder having an output. A multiplexer is optionally coupled to the first and second encoder portions and responsive to a predetermined signal from the second encoder portion to select signals from the outputs of one of the first and second encoders. A pair of buffers are optionally provided, a first buffer coupled between the output of the sample-and-hold circuit and both the polarity reverser and the zero crossing detector and a second buffer coupled between the output of the sample-and-hold circuit and the second array of comparators. First and second switches are optionally provided, the first switches being operational only during a first repeating time window for coupling the first buffer to the zero crossing detector and the polarity reverser and coupling the second buffer to the second array of comparators and the second switches are operational only during a second repeating time window not overlapping the first time window for coupling said second buffer to said zero crossing detector and said polarity reverser.

摘要翻译： 一种A / D转换器，其包括具有输入和输出的采样和保持电路，过零检测器，具有耦合到采样保持电路的输出的输入端，并具有指示变化的输出 输入信号的极性和具有耦合到采样保持电路的输出的输入的极性反转器，耦合到过零检测器的输出端和输出端子的控制端子。 优选地具有第一和第二阵列的比较器组各自具有分别耦合到极性反相器的输出的输入，每个比较器具有输出。 优选地具有第一和第二部分的编码器耦合到比较器的输出端，第一阵列优选地耦合到第一编码器部分，而第二阵列优选地耦合到第二编码器部分，编码器具有输出。 复用器可选地耦合到第一和第二编码器部分，并且响应于来自第二编码器部分的预定信号来选择来自第一和第二编码器之一的输出的信号。 可选地提供一对缓冲器，第一缓冲器耦合在采样保持电路的输出端与极性反相器和过零检测器两者之间，第二缓冲器耦合在采样保持电路的输出和 第二组比较器。 可选地提供第一和第二开关，第一开关仅在第一重复时间窗口期间操作，用于将第一缓冲器耦合到过零检测器和极性反相器，并将第二缓冲器耦合到第二比较器阵列，并且第二开关 仅在与第一时间窗口不重叠的第二重复时间窗口中操作，用于将所述第二缓冲器耦合到所述过零检测器和所述极性反转器。

公开(公告)号：US06404262B1

公开(公告)日：2002-06-11

申请号：US09715661

申请日：2000-11-17

申请人： Krishnaswamy Nagaraj ,  T. R. Viswanathan

发明人： Krishnaswamy Nagaraj ,  T. R. Viswanathan

IPC分类号： G06F764

CPC分类号： G06G7/184

摘要： An exemplary electronic circuit of the present include first and second buffers 34 and 38, which are preferably unity gain buffers. A first switch 36 (e.g., a NMOS transistor or a CMOS transmission gate) is coupled between the output of the first buffer 34 and the first terminal of a capacitor 40. The input of the second buffer 38 is also coupled to the first terminal of the capacitor 40. A second switch 42 is coupled between the second terminal of the capacitor 40 and a first voltage node Va and a third switch 44 is coupled between the second terminal of the capacitor 40 and a second voltage node Vb. This circuit can be used as an integrator in a number of applications.

摘要翻译： 本发明的示例性电子电路包括第一和第二缓冲器34和38，其优选地是单位增益缓冲器。 第一开关36（例如，NMOS晶体管或CMOS传输门）耦合在第一缓冲器34的输出端与电容器40的第一端之间。第二缓冲器38的输入端还耦合到 电容器40.第二开关42耦合在电容器40的第二端和第一电压节点Va之间，第三开关44耦合在电容器40的第二端和第二电压节点Vb之间。 该电路可用作许多应用中的积分器。

公开(公告)号：US06188345B1

公开(公告)日：2001-02-13

申请号：US09050444

申请日：1998-03-30

申请人： Charles L. McDonald ,  T. R. Viswanathan ,  Krishnaswamy Nagaraj

发明人： Charles L. McDonald ,  T. R. Viswanathan ,  Krishnaswamy Nagaraj

IPC分类号： H03M300

CPC分类号： H03M3/412 ,  H03M3/456

摘要： A high speed sigma-delta A/D converter for a sequence of analog samples xn (n=0,1,2, . . . N−1) has an input, a plurality N−1 of phase clocks &PHgr;n, a plurality of sample-hold circuits 40n, a plurality N−1 of circuit stages, and a D/A converter. The input receives the analog samples xn. The sample-hold circuits 40n are coupled to the input and each responds to a respective phase clock &PHgr;n to sample and hold a corresponding analog sample Xn. Each circuit stage n has a summer 42n and a quantizer 44n. The summer has (i) a data input receiving a data signal (xn) from a corresponding sample-hold circuit 40n, (ii) a prior sum signal (wn−1) input, and (iii) a prior quantized signal (yn−1) negative input. The summer 42n produces a sum signal (wn=xn+wn−−Yn−1) at a summer output. The quantizer 44n is coupled to the summer's output for quantizing the sum signal wn into a quantized sum signal yn. The D/A converter provides the N−1 (last) stage's quantized sum signal yN−1 to the prior sum signal input of the 0 (first) stage's summer 421.

摘要翻译： 用于一系列模拟样本xn（n = 0,1,2，...，N-1）的高速Σ-ΔA/ D转换器具有输入，多个N-1个相位时钟＆amp; 多个采样保持电路40n，多个N-1个电路级和D / A转换器。 输入接收模拟样本xn。 采样保持电路40n耦合到输入端，并且每个响应相应的相位时钟＆phgr; n以采样并保持对应的模拟采样Xn。 每个电路级n具有加法器42n和量化器44n。 夏季具有（i）从对应的采样保持电路40n接收数据信号（xn）的数据输入，（ii）输入的先验和信号（wn-1），以及（iii）先前的量化信号（yn- 1）负输入。 夏季42n在夏季输出时产生和信号（wn = xn + wn-Yn-1）。 量化器44n耦合到夏季输出，用于将和信号wn量化为量化和信号yn。 D / A转换器将N-1（最后）级的量化和信号yN-1提供给0（第一级）的加法器421的先前求和信号输入。

公开(公告)号：US06515605B2

公开(公告)日：2003-02-04

申请号：US09846429

申请日：2001-04-30

申请人： Carl M. Panasik ,  T. R. Viswanathan

发明人： Carl M. Panasik ,  T. R. Viswanathan

IPC分类号： H03M300

CPC分类号： H03M3/50

摘要： A wireless base station having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a base station 300 that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period. An summer is coupled to each digital-to-analog converter (120, 122, 124, 126) for summing each output from each digital-to-analog converter (120, 122, 124, 126) to generate an analog output. Hereby, the digital-to-analog conversion circuit (105) according to the invention emulates a delta-sigma digital-to-analog converter having both high speed and high resolution.

摘要翻译： 一种无线基站，其具有可以比以前可实现的更高速度操作的改进的DAC，其以不同的方式利用了Σ-Δ原理。 更具体地说，本发明包括实现数模转换电路（105）的基站300，数字 - 模拟转换电路（105）包括诸如只读存储器的存储装置（110），用于存储对应于所有可能值的Δ-Σ模拟序列 耦合到多个一位数模转换器（120,122,124,126）的数字输入（106）。 每个数模转换器（120,122,124,126）由多相时钟计时，使得施加到数模转换器（120,122,124,126中的每一个）的每个相位 ）在过采样期间相对于彼此延迟。 加法器耦合到每个数模转换器（120,122,124,126），用于对来自每个数模转换器（120,122,124,126）的每个输出求和以产生模拟输出。 因此，根据本发明的数模转换电路（105）模拟具有高速和高分辨率的三角形数模转换器。