公开(公告)号：US06188345B1

公开(公告)日：2001-02-13

申请号：US09050444

申请日：1998-03-30

申请人： Charles L. McDonald ,  T. R. Viswanathan ,  Krishnaswamy Nagaraj

发明人： Charles L. McDonald ,  T. R. Viswanathan ,  Krishnaswamy Nagaraj

IPC分类号： H03M300

CPC分类号： H03M3/412 ,  H03M3/456

摘要： A high speed sigma-delta A/D converter for a sequence of analog samples xn (n=0,1,2, . . . N−1) has an input, a plurality N−1 of phase clocks &PHgr;n, a plurality of sample-hold circuits 40n, a plurality N−1 of circuit stages, and a D/A converter. The input receives the analog samples xn. The sample-hold circuits 40n are coupled to the input and each responds to a respective phase clock &PHgr;n to sample and hold a corresponding analog sample Xn. Each circuit stage n has a summer 42n and a quantizer 44n. The summer has (i) a data input receiving a data signal (xn) from a corresponding sample-hold circuit 40n, (ii) a prior sum signal (wn−1) input, and (iii) a prior quantized signal (yn−1) negative input. The summer 42n produces a sum signal (wn=xn+wn−−Yn−1) at a summer output. The quantizer 44n is coupled to the summer's output for quantizing the sum signal wn into a quantized sum signal yn. The D/A converter provides the N−1 (last) stage's quantized sum signal yN−1 to the prior sum signal input of the 0 (first) stage's summer 421.

摘要翻译： 用于一系列模拟样本xn（n = 0,1,2，...，N-1）的高速Σ-ΔA/ D转换器具有输入，多个N-1个相位时钟＆amp; 多个采样保持电路40n，多个N-1个电路级和D / A转换器。 输入接收模拟样本xn。 采样保持电路40n耦合到输入端，并且每个响应相应的相位时钟＆phgr; n以采样并保持对应的模拟采样Xn。 每个电路级n具有加法器42n和量化器44n。 夏季具有（i）从对应的采样保持电路40n接收数据信号（xn）的数据输入，（ii）输入的先验和信号（wn-1），以及（iii）先前的量化信号（yn- 1）负输入。 夏季42n在夏季输出时产生和信号（wn = xn + wn-Yn-1）。 量化器44n耦合到夏季输出，用于将和信号wn量化为量化和信号yn。 D / A转换器将N-1（最后）级的量化和信号yN-1提供给0（第一级）的加法器421的先前求和信号输入。