发明授权
US07321634B2 Method and apparatus for variable sigma-delta modulation 有权
用于可变Σ-Δ调制的方法和装置

Method and apparatus for variable sigma-delta modulation
摘要:
A method and apparatus for modulating a digital input signal is disclosed. The digital input signal is partitioned into a less-significant bit signal and a more-significant bit signal. A lower-order modulation of the less-significant bit signal is performed to generate an intermediate output signal. The intermediate output signal is appended to the more-significant bit signal to form an intermediate input signal. A higher-order modulation of the intermediate input signal is performed to generate a digital output signal. The higher-order modulation is of an order higher than the lower-order modulation. A phase-locked loop using the method and apparatus is disclosed.
公开/授权文献
信息查询
0/0