发明授权
- 专利标题: Method and apparatus for variable sigma-delta modulation
- 专利标题(中): 用于可变Σ-Δ调制的方法和装置
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申请号: US11015608申请日: 2004-12-17
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公开(公告)号: US07321634B2公开(公告)日: 2008-01-22
- 发明人: Herbert L. Ko
- 申请人: Herbert L. Ko
- 申请人地址: SG Singapore
- 专利权人: Verigy (Singapore) Pte. Ltd.
- 当前专利权人: Verigy (Singapore) Pte. Ltd.
- 当前专利权人地址: SG Singapore
- 主分类号: H04L27/00
- IPC分类号: H04L27/00
摘要:
A method and apparatus for modulating a digital input signal is disclosed. The digital input signal is partitioned into a less-significant bit signal and a more-significant bit signal. A lower-order modulation of the less-significant bit signal is performed to generate an intermediate output signal. The intermediate output signal is appended to the more-significant bit signal to form an intermediate input signal. A higher-order modulation of the intermediate input signal is performed to generate a digital output signal. The higher-order modulation is of an order higher than the lower-order modulation. A phase-locked loop using the method and apparatus is disclosed.
公开/授权文献
- US20060133517A1 Method and apparatus for variable sigma-delta modulation 公开/授权日:2006-06-22
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