公开(公告)号：US08790975B2

公开(公告)日：2014-07-29

申请号：US13040975

申请日：2011-03-04

Applicant: Peter Baars ,  Till Schloesser ,  Vivien Schroeder

Inventor： Peter Baars ,  Till Schloesser ,  Vivien Schroeder

IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  H01L27/108

CPC classification number: H01L21/76877 ,  H01L21/02697 ,  H01L21/28 ,  H01L23/5223 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/87 ,  H01L28/91 ,  H01L29/665 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.

Abstract translation: 当在诸如动态RAM区域的金属化系统中形成电容结构时，可以与“规则”金属特征一起形成占位符金属区域，从而实现非常有效的整体工艺流程。 在某个制造阶段，可以基于湿式化学蚀刻配方去除占位金属区域的金属，随后沉积用于电容结构的电极材料和电介质材料，而不会过度影响金属化系统的其它部分 。 以这种方式，可以在非常有效的总体制造流程的基础上实现非常高的电容值。

公开(公告)号：US20120223412A1

公开(公告)日：2012-09-06

申请号：US13040975

申请日：2011-03-04

Applicant: Peter Baars ,  Till Schloesser ,  Vivien Schroeder

Inventor： Peter Baars ,  Till Schloesser ,  Vivien Schroeder

IPC: H01L29/02 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/76877 ,  H01L21/02697 ,  H01L21/28 ,  H01L23/5223 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/87 ,  H01L28/91 ,  H01L29/665 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.

Abstract translation: 当在诸如动态RAM区域的金属化系统中形成电容结构时，可以与“规则”金属特征一起形成占位符金属区域，从而实现非常有效的整体工艺流程。 在某个制造阶段，可以基于湿式化学蚀刻配方去除占位金属区域的金属，随后沉积用于电容结构的电极材料和电介质材料，而不会过度影响金属化系统的其它部分 。 以这种方式，可以在非常有效的总体制造流程的基础上实现非常高的电容值。

公开(公告)号：US20120248551A1

公开(公告)日：2012-10-04

申请号：US13079492

申请日：2011-04-04

Applicant: Peter Baars ,  Marco Lepper ,  Uwe Kahler ,  Vivien Schroeder

Inventor： Peter Baars ,  Marco Lepper ,  Uwe Kahler ,  Vivien Schroeder

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L21/2855 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/32134 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.

Abstract translation: 在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光，然后清洗并应用Aqua Regia的第二次应用来减少。 实施例包括在半导体衬底上溅射沉积Ni / Pt层，退火Ni / Pt层，湿剥离未反应的Ni，退火Ni剥离的Ni / Pt层，从退火的Ni / Pt层剥离未反应的Pt，例如， Aqua Regia，用氧等离子体处理Pt剥离的Ni / Pt层，清洁Ni / Pt层，以及从清洁的Ni / Pt层剥离未反应的Pt，例如，通过第二次应用Aqua Regia。

公开(公告)号：US08883586B2

公开(公告)日：2014-11-11

申请号：US13079492

申请日：2011-04-04

Applicant: Peter Baars ,  Marco Lepper ,  Uwe Kahler ,  Vivien Schroeder

Inventor： Peter Baars ,  Marco Lepper ,  Uwe Kahler ,  Vivien Schroeder

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/2855 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/32134 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.

Abstract translation: 在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光，然后清洗并应用Aqua Regia的第二次应用来减少。 实施例包括在半导体衬底上溅射沉积Ni / Pt层，退火Ni / Pt层，湿剥离未反应的Ni，退火Ni剥离的Ni / Pt层，从退火的Ni / Pt层剥离未反应的Pt，例如， Aqua Regia，用氧等离子体处理Pt剥离的Ni / Pt层，清洁Ni / Pt层，以及从清洁的Ni / Pt层剥离未反应的Pt，例如，通过第二次应用Aqua Regia。

公开(公告)号：US08247281B2

公开(公告)日：2012-08-21

申请号：US12822789

申请日：2010-06-24

Applicant: Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

Inventor： Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

IPC: H01L21/8238

CPC classification number: H01L21/823425 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/7843

Abstract: In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

Abstract translation: 在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。 因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。

公开(公告)号：US20100301427A1

公开(公告)日：2010-12-02

申请号：US12785185

申请日：2010-05-21

Applicant: Markus Lenski ,  Klaus Hempel ,  Vivien Schroeder ,  Robert Binder ,  Joachim Metzger

Inventor： Markus Lenski ,  Klaus Hempel ,  Vivien Schroeder ,  Robert Binder ,  Joachim Metzger

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: In a replacement gate approach in sophisticated semiconductor devices, a tantalum nitride etch stop material may be efficiently removed on the basis of a wet chemical etch recipe using ammonium hydroxide. Consequently, a further work function adjusting material may be formed with superior uniformity, while the efficiency of the subsequent adjusting of the work function may also be increased. Thus, superior uniformity, i.e., less pronounced transistor variability, may be accomplished on the basis of a replacement gate approach in which the work function of the gate electrodes of P-channel transistors and N-channel transistors is adjusted after completing the basic transistor configuration.

Abstract translation: 在复杂半导体器件中的替代栅极方法中，可以基于使用氢氧化铵的湿化学蚀刻配方有效地去除氮化钽蚀刻停止材料。 因此，可以形成具有优异均匀性的另外的功能调节材料，同时可以提高随后的功函数调整的效率。 因此，可以在替代栅极方法的基础上实现优异的均匀性，即较不明显的晶体管可变性，其中在完成基本晶体管配置之后调节P沟道晶体管和N沟道晶体管的栅电极的功函数 。

公开(公告)号：US08679924B2

公开(公告)日：2014-03-25

申请号：US13017558

申请日：2011-01-31

Applicant: Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

Inventor： Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.

Abstract translation: 可以基于设置在掩模材料中的栅极开口或栅极沟槽形成体构造的三维晶体管。 因此，可以在由栅极开口限定的部分中的底层有源区域中有效地图案化自对准半导体鳍片，同时可以有效地屏蔽其中的栅极开口，其中将提供平面晶体管。 在图案化半导体鳍片并调整其有效高度之后，可以基于通常应用于平面晶体管和三维晶体管的工艺技术来继续进一步的处理。

公开(公告)号：US20110291196A1

公开(公告)日：2011-12-01

申请号：US13017558

申请日：2011-01-31

Applicant: Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

Inventor： Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.

Abstract translation: 可以基于设置在掩模材料中的栅极开口或栅极沟槽形成体构造的三维晶体管。 因此，可以在由栅极开口限定的部分中的底层有源区域中有效地图案化自对准半导体鳍片，同时可以有效地屏蔽其中的栅极开口，其中将提供平面晶体管。 在图案化半导体鳍片并调整其有效高度之后，可以基于通常应用于平面晶体管和三维晶体管的工艺技术来继续进一步的处理。

公开(公告)号：US20120282764A1

公开(公告)日：2012-11-08

申请号：US13550435

申请日：2012-07-16

Applicant: Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

Inventor： Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

IPC: H01L21/283 ,  H01L21/302

CPC classification number: H01L21/823425 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/7843

Abstract: In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

Abstract translation: 在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。 因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。

公开(公告)号：US08357575B2

公开(公告)日：2013-01-22

申请号：US13550435

申请日：2012-07-16

Applicant: Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

Inventor： Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

IPC: H01L21/8238

CPC classification number: H01L21/823425 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/7843

Abstract: In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

Abstract translation: 在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。 因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。