Invention Grant
US08247281B2 Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers
有权
通过改变应力介电覆盖层的去除速率，在替代浇口方法中暴露占位符材料的技术
- Patent Title: Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers
- Patent Title (中): 通过改变应力介电覆盖层的去除速率，在替代浇口方法中暴露占位符材料的技术
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Application No.: US12822789Application Date: 2010-06-24
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Publication No.: US08247281B2Publication Date: 2012-08-21
- Inventor: Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
- Applicant: Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
- Applicant Address: KY Grand Cayman
- Assignee: GlobalFoundries, Inc.
- Current Assignee: GlobalFoundries, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102009031113 20090630
- Main IPC: H01L21/8238
- IPC: H01L21/8238
Abstract:
In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.
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