公开(公告)号：US08951901B2

公开(公告)日：2015-02-10

申请号：US13188745

申请日：2011-07-22

Applicant: Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

Inventor： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.

Abstract translation: 在复杂的半导体器件中，可以通过形成底切门配置来实现在早期制造阶段中提供的诸如高k电介质材料和含金属电极材料的敏感栅极材料的封装。 为此，在栅极层叠层的基本图案化之后施加湿化学蚀刻序列，其中至少以交替的方式进行基于臭氧和基于氢氟酸的工艺步骤，从而实现基本上自限制的去除行为 。

公开(公告)号：US08524591B2

公开(公告)日：2013-09-03

申请号：US12848644

申请日：2010-08-02

Applicant: Sven Beyer ,  Rick Carter ,  Andreas Hellmich ,  Berthold Reimer

Inventor： Sven Beyer ,  Rick Carter ,  Andreas Hellmich ,  Berthold Reimer

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28247 ,  H01L21/0206 ,  H01L21/02244 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

Abstract: In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.

Abstract translation: 在半导体器件中，通过在形成薄的氮化硅基材料之后将材料暴露于氧等离子体，可以提高氮化钛材料的完整性。 氧等离子体可能导致任何微小表面部分的附加钝化，这些微小表面部分可能不被氮化硅基材料适当地覆盖。 因此，可以在附加钝化之后进行有效的清洁配方，例如基于SPM的清洁方法，而不会导致氮化钛材料的不适当的材料损失。 以这种方式，可以在有效的清洁过程的基础上形成具有非常薄的保护衬垫材料的复杂的高k金属栅极堆叠，而不会在早期制造阶段中过度地造成显着的产量损失。

公开(公告)号：US20130203244A1

公开(公告)日：2013-08-08

申请号：US13368055

申请日：2012-02-07

Applicant: Joanna Wasyluk ,  Stephan Kronholz ,  Yew-Tuck Chow ,  Richard J. Carter ,  Berthold Reimer ,  Kai Tern Sih

Inventor： Joanna Wasyluk ,  Stephan Kronholz ,  Yew-Tuck Chow ,  Richard J. Carter ,  Berthold Reimer ,  Kai Tern Sih

IPC: H01L21/20

CPC classification number: H01L21/30604 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.

Abstract translation: 公开了一种用于制造集成电路的方法，其包括根据实施例提供包括p型场效应晶体管（pFET）的集成电路，使用氨 - 过氧化氢 - 水（pFET）凹陷pFET的表面区域 APM）溶液以形成凹陷的pFET表面区域，以及在凹陷的pFET表面区域上沉积硅基材料通道。

公开(公告)号：US20130126984A1

公开(公告)日：2013-05-23

申请号：US13301981

申请日：2011-11-22

Applicant: Berthold Reimer ,  Martin Trentzsch ,  Erwin Grund ,  Sven Beyer

Inventor： Berthold Reimer ,  Martin Trentzsch ,  Erwin Grund ,  Sven Beyer

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/02244 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76807 ,  H01L29/4966

Abstract: When patterning metal-containing material layers, such as titanium nitride, in critical manufacturing stages, for instance upon forming sophisticated high-k metal gate electrode structures or providing hard mask materials for patterning a metallization system, the surface adhesion of a resist material on the titanium nitride material may be improved by applying a controlled oxidation process.

Abstract translation: 当在关键制造阶段中，例如在形成复杂的高k金属栅极电极结构或提供用于图案化金属化系统的硬掩模材料时，将诸如氮化钛的含金属材料层图案化时，抗蚀剂材料在 可以通过施加受控氧化工艺来改善氮化钛材料。

公开(公告)号：US08283232B2

公开(公告)日：2012-10-09

申请号：US12785849

申请日：2010-05-24

Applicant: Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

Inventor： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/513 ,  H01L29/66583 ,  H01L29/7833

Abstract: A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.

Abstract translation: 栅极电极结构可以基于氮化硅帽材料与非常薄且均匀的基于氧化硅的蚀刻停止材料组合形成，其可以基于化学驱动的氧化工艺形成。 由于厚度减小，可以避免例如在门图案化之后的湿化学清洁过程期间显着的材料侵蚀，从而不会过度影响进一步的加工，例如关于形成嵌入式应变诱导半导体合金， 同时在去除氮化硅帽材料期间提供期望的蚀刻停止能力。

公开(公告)号：US08247281B2

公开(公告)日：2012-08-21

申请号：US12822789

申请日：2010-06-24

Applicant: Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

Inventor： Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

IPC: H01L21/8238

CPC classification number: H01L21/823425 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/7843

Abstract: In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

Abstract translation: 在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。 因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。

公开(公告)号：US20130203245A1

公开(公告)日：2013-08-08

申请号：US13564071

申请日：2012-08-01

Applicant: Joanna WASYLUK ,  Stephan KRONHOLZ ,  Berthold Reimer ,  Sven Metzger ,  Gregory Nowling ,  John Foster ,  Paul Besser

Inventor： Joanna WASYLUK ,  Stephan KRONHOLZ ,  Berthold Reimer ,  Sven Metzger ,  Gregory Nowling ,  John Foster ,  Paul Besser

IPC: H01L21/20

CPC classification number: H01L21/02057 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878

Abstract: A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

Abstract translation: 一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。 第一部分和第二部分由浅沟槽隔离特征电隔离。 该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。 提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。 该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

公开(公告)号：US08445344B2

公开(公告)日：2013-05-21

申请号：US12787461

申请日：2010-05-26

Applicant: Richard Carter ,  Falk Graetsch ,  Martin Trentzsch ,  Sven Beyer ,  Berthold Reimer ,  Robert Binder ,  Boris Bayha

Inventor： Richard Carter ,  Falk Graetsch ,  Martin Trentzsch ,  Sven Beyer ,  Berthold Reimer ,  Robert Binder ,  Boris Bayha

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

Abstract translation: 在基本上相同的构造的基础上对N沟道晶体管和P沟道晶体管的复杂的栅电极结构进行构图，然而，可以在早期制造阶段完成功函数调整。 为此，在将期望的功函数金属物质并入高k电介质材料中之后去除扩散层和覆盖层材料，随后沉积公共栅层堆叠并随后构图。

公开(公告)号：US20130122716A1

公开(公告)日：2013-05-16

申请号：US13295497

申请日：2011-11-14

Applicant: Berthold Reimer ,  Claudia Wolf

Inventor： Berthold Reimer ,  Claudia Wolf

IPC: H01L21/306

CPC classification number: H01L21/31111 ,  H01L21/67086

Abstract: Disclosed herein are methods of controlling the etching of a layer of silicon nitride relative to a layer of silicon dioxide. In one illustrative example, the method includes providing an etch bath that is comprised of an existing etchant adapted to selectively etch silicon nitride relative to silicon dioxide, performing an etching process in the etch bath using the existing etchant to selectively remove a silicon nitride material positioned above a silicon dioxide material on a plurality of semiconducting substrates, determining an amount of the existing etchant to be removed based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath and determining an amount of new etchant to be added to the etch bath based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath.

Abstract translation: 本文公开了控制氮化硅层相对于二氧化硅层的蚀刻的方法。 在一个说明性示例中，该方法包括提供蚀刻槽，其由现有蚀刻剂组成，其适于相对于二氧化硅选择性地蚀刻氮化硅，使用现有蚀刻剂在蚀刻槽中执行蚀刻工艺，以选择性地去除定位的氮化硅材料 在多个半导体衬底上方的二氧化硅材料上方，通过在蚀刻槽中蚀刻多个衬底，基于蚀刻槽的每个衬底硅负载确定待除去的现有蚀刻剂的量，并且确定 通过在蚀刻槽中蚀刻多个衬底，基于蚀刻浴的每个衬底硅负载而添加到蚀刻槽中的新蚀刻剂。

公开(公告)号：US08357575B2

公开(公告)日：2013-01-22

申请号：US13550435

申请日：2012-07-16

Applicant: Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

Inventor： Klaus Hempel ,  Patrick Press ,  Vivien Schroeder ,  Berthold Reimer ,  Johannes Groschopf

IPC: H01L21/8238

CPC classification number: H01L21/823425 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/7843

Abstract: In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

Abstract translation: 在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。 因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。