MOL INSITU PT REWORK SEQUENCE
    1.
    发明申请
    MOL INSITU PT REWORK SEQUENCE 有权
    MOL INSITU PT REWORK序列

    公开(公告)号:US20120248551A1

    公开(公告)日:2012-10-04

    申请号:US13079492

    申请日:2011-04-04

    IPC分类号: H01L29/772 H01L21/28

    摘要: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.

    摘要翻译: 在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光,然后清洗并应用Aqua Regia的第二次应用来减少。 实施例包括在半导体衬底上溅射沉积Ni / Pt层,退火Ni / Pt层,湿剥离未反应的Ni,退火Ni剥离的Ni / Pt层,从退火的Ni / Pt层剥离未反应的Pt,例如, Aqua Regia,用氧等离子体处理Pt剥离的Ni / Pt层,清洁Ni / Pt层,以及从清洁的Ni / Pt层剥离未反应的Pt,例如,通过第二次应用Aqua Regia。

    Method for fabricating an integrated circuit device with through-plating elements and terminal units
    3.
    发明申请
    Method for fabricating an integrated circuit device with through-plating elements and terminal units 有权
    用于制造具有贯通电镀元件和端子单元的集成电路器件的方法

    公开(公告)号:US20050073046A1

    公开(公告)日:2005-04-07

    申请号:US10937903

    申请日:2004-09-10

    CPC分类号: H01L21/76877

    摘要: A method for fabricating an integrated circuit device, an electrically conductive substrate being provided, an insulation layer being deposited on the substrate, the insulation layer being etched in structures, a contact-making layer being deposited on the patterned insulation layer and on the substrate in depressions which have first and second lateral dimensions, the contact-making layer being etched back in such a way that the contact-making layer is preserved in the structures with the depressions which have first lateral dimensions of the order of magnitude of the structure depth of the insulation layer and the contact-making layer is removed in the structures with depressions which have second lateral dimensions significantly greater than the structure depth of the insulation layer.

    摘要翻译: 一种制造集成电路器件的方法,提供导电衬底,绝缘层沉积在衬底上,绝缘层在结构上被蚀刻,接触层沉积在图案化的绝缘层上和衬底上 凹陷具有第一和第二横向尺寸,接触层被回蚀,使接触层保留在具有第一横向尺寸为结构深度的数量级的凹陷的结构中 在具有凹陷的结构中去除绝缘层和接触层,所述凹陷具有明显大于绝缘层的结构深度的第二横向尺寸。

    Mol insitu Pt rework sequence
    4.
    发明授权
    Mol insitu Pt rework sequence 有权
    莫尔实验Pt返修序列

    公开(公告)号:US08883586B2

    公开(公告)日:2014-11-11

    申请号:US13079492

    申请日:2011-04-04

    摘要: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.

    摘要翻译: 在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光,然后清洗并应用Aqua Regia的第二次应用来减少。 实施例包括在半导体衬底上溅射沉积Ni / Pt层,退火Ni / Pt层,湿剥离未反应的Ni,退火Ni剥离的Ni / Pt层,从退火的Ni / Pt层剥离未反应的Pt,例如, Aqua Regia,用氧等离子体处理Pt剥离的Ni / Pt层,清洁Ni / Pt层,以及从清洁的Ni / Pt层剥离未反应的Pt,例如,通过第二次应用Aqua Regia。

    Method for fabricating an integrated circuit device with through-plating elements and terminal units
    6.
    发明授权
    Method for fabricating an integrated circuit device with through-plating elements and terminal units 有权
    用于制造具有贯通电镀元件和端子单元的集成电路器件的方法

    公开(公告)号:US07115501B2

    公开(公告)日:2006-10-03

    申请号:US10937903

    申请日:2004-09-10

    IPC分类号: H01L21/4763

    CPC分类号: H01L21/76877

    摘要: A method for fabricating an integrated circuit device, an electrically conductive substrate being provided, an insulation layer being deposited on the substrate, the insulation layer being etched in structures, a contact-making layer being deposited on the patterned insulation layer and on the substrate in depressions which have first and second lateral dimensions, the contact-making layer being etched back in such a way that the contact-making layer is preserved in the structures with the depressions which have first lateral dimensions of the order of magnitude of the structure depth of the insulation layer and the contact-making layer is removed in the structures with depressions which have second lateral dimensions significantly greater than the structure depth of the insulation layer.

    摘要翻译: 一种制造集成电路器件的方法,提供导电衬底,绝缘层沉积在衬底上,绝缘层在结构上被蚀刻,接触层沉积在图案化的绝缘层上和衬底上 凹陷具有第一和第二横向尺寸,接触层被回蚀,使接触层保留在具有第一横向尺寸为结构深度的数量级的凹陷的结构中 在具有凹陷的结构中去除绝缘层和接触层,所述凹陷具有明显大于绝缘层的结构深度的第二横向尺寸。