Method for fabricating a semiconductor structure
    5.
    发明授权
    Method for fabricating a semiconductor structure 失效
    半导体结构的制造方法

    公开(公告)号:US06964912B2

    公开(公告)日:2005-11-15

    申请号:US10721752

    申请日:2003-11-26

    CPC classification number: H01L27/10867

    Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate, providing a plurality of trenches in the semiconductor substrate using a first hard mask, and causing the hard mask to recede by a predetermined distance with respect to the trench wall at the top side of the semiconductor substrate for forming a first hard mask that has been caused to recede. An isolation trench structure is provided in the semiconductor substrate using a second hard mask, the isolation trench structure subdividing the first first hard mask that has been caused to recede along rows into strip sections and the strip sections of adjacent rows being arranged offset with respect to one another. The receding process results in a reduction of an overlap region between two strip sections of adjacent rows in comparison with an overlap region which would be present without the receding process. The second hard mask is removed and the isolation trench structure is filled and planarized with a filling material using the first hard mask subdivided into the strip sections.

    Abstract translation: 一种制造半导体结构的方法包括:提供半导体衬底,使用第一硬掩模在半导体衬底中提供多个沟槽,并使硬掩模相对于沟槽壁的顶侧相对于沟槽壁后退预定距离 用于形成已经退化的第一硬掩模的半导体衬底。 使用第二硬掩模在所述半导体衬底中提供隔离沟槽结构,所述隔离沟槽结构将已经被排成一行的所述第一第一硬掩模细分成条形部分,并且相邻行的条带部分相对于 另一个。 后退过程导致相邻行的两个条状部分之间的重叠区域与不存在后退处理的重叠区域相比会减少。 去除第二硬掩模,并且使用被细分为条带部分的第一硬掩模用填充材料填充和平坦化隔离沟槽结构。

    Method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module
    7.
    发明授权
    Method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module 失效
    用于在半导体模块中产生用于n沟道场效应晶体管和p沟道场效应晶体管的浅沟槽隔离的方法

    公开(公告)号:US06770530B2

    公开(公告)日:2004-08-03

    申请号:US10385000

    申请日:2003-03-10

    CPC classification number: H01L21/76224 H01L21/823878

    Abstract: The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.

    Abstract translation: 用于在半导体模块中产生n沟道场效应晶体管和p沟道场效应晶体管的浅沟槽隔离的方法提供以下步骤。 在隔离沟槽中施加热氧化层。 随后施加氮化物衬垫。 在另一步骤中,在要制造n沟道场效应晶体管的区域中施加掩模。 在掩模周围除去氮化物衬垫。 最后,面具也被删除。 结果,提高了n沟道场效应晶体管的性质,而不损害p沟道场效应晶体管的性质。

    Method for masking a recess in a structure having a high aspect ratio
    8.
    发明授权
    Method for masking a recess in a structure having a high aspect ratio 有权
    用于掩蔽具有高纵横比的结构中的凹部的方法

    公开(公告)号:US07261829B2

    公开(公告)日:2007-08-28

    申请号:US10501464

    申请日:2003-01-08

    CPC classification number: H01L21/0337

    Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.

    Abstract translation: 描述了用于选择性掩蔽的方法。 在这种情况下,填充材料被应用于当纵横比高时作为结构的纵横比的函数形成空腔的结构。 然后将填充层移除至空腔,并且使用蚀刻工艺,从形成空腔的凹部完全去除填充材料。 以这种方式,区域被选择性地暴露。

    Method for masking a recess in a structure with a large aspect ratio
    9.
    发明申请
    Method for masking a recess in a structure with a large aspect ratio 有权
    用于掩蔽具有大纵横比的结构中的凹部的方法

    公开(公告)号:US20050224451A1

    公开(公告)日:2005-10-13

    申请号:US10501464

    申请日:2003-01-08

    CPC classification number: H01L21/0337

    Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.

    Abstract translation: 描述了用于选择性掩蔽的方法。 在这种情况下,填充材料被应用于当纵横比高时作为结构的纵横比的函数形成空腔的结构。 然后将填充层移除至空腔,并且使用蚀刻工艺,从形成空腔的凹部完全去除填充材料。 以这种方式,区域被选择性地暴露。

    Method for filling depressions on a semiconductor wafer
    10.
    发明授权
    Method for filling depressions on a semiconductor wafer 有权
    用于在半导体晶片上填充凹陷的方法

    公开(公告)号:US06716720B2

    公开(公告)日:2004-04-06

    申请号:US10378244

    申请日:2003-03-03

    CPC classification number: H01L21/76224 H01L21/31056

    Abstract: A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.

    Abstract translation: 公开了一种用于填充两个垂直相邻的半导体层之间的凹陷的方法,特别是在隔离沟槽形成的上下文中出现的边缘凹陷。 优选由氧化硅制成的覆盖层以大面积方式沉积,然后基本上在层的整个深度上掺杂掺杂材料,优选氮。 掺杂材料提供了增加的覆盖层去除率,使得在去除工艺之后,覆盖层材料仅保留在凹陷中。

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