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公开(公告)号:US20210327754A1
公开(公告)日:2021-10-21
申请号:US17359068
申请日:2021-06-25
发明人: Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号: H01L21/768 , H01L21/285 , H01L27/105 , H01L27/108 , C23C16/04 , H01L21/3213
摘要: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
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公开(公告)号:US11075115B2
公开(公告)日:2021-07-27
申请号:US16124050
申请日:2018-09-06
发明人: Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号: H01L21/768 , H01L21/285 , H01L27/105 , H01L27/108 , C23C16/04 , H01L21/3213 , H01L21/321
摘要: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
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公开(公告)号:US20190326168A1
公开(公告)日:2019-10-24
申请号:US16457353
申请日:2019-06-28
发明人: Tsung-Han Yang , Anand Chandrashekar , Jasmine Lin , Deqi Wang , Gang Liu , Michal Danek , Siew Neo
IPC分类号: H01L21/768 , H01L21/285 , C23C16/04 , H01L27/108 , H01L21/321 , C23C16/06
摘要: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.
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公开(公告)号:US20190019725A1
公开(公告)日:2019-01-17
申请号:US16124050
申请日:2018-09-06
发明人: Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号: H01L21/768 , H01L27/108 , C23C16/04 , H01L27/105 , H01L21/285 , H01L21/3213 , H01L21/321
摘要: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
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公开(公告)号:US20160190008A1
公开(公告)日:2016-06-30
申请号:US14965806
申请日:2015-12-10
发明人: Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号: H01L21/768
CPC分类号: H01L21/76879 , C23C16/045 , H01L21/28556 , H01L21/28562 , H01L21/321 , H01L21/32133 , H01L21/32136 , H01L21/7685 , H01L21/76865 , H01L21/76874 , H01L21/76876 , H01L21/76877 , H01L21/76883 , H01L21/76898 , H01L27/1052 , H01L27/10891
摘要: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
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公开(公告)号:US08835317B2
公开(公告)日:2014-09-16
申请号:US13888077
申请日:2013-05-06
IPC分类号: H01L21/44 , H01L21/48 , H01L21/768 , H01L21/285 , H01L21/3213
CPC分类号: H01L21/486 , H01L21/28556 , H01L21/32136 , H01L21/76865 , H01L21/76877
摘要: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.
摘要翻译: 提供了以基本上无空隙的方式用含钨材料填充高纵横比特征的方法和装置。 在某些实施方案中,该方法包括沉积含钨材料的初始层,然后选择性地去除初始层的一部分以形成沿着高纵横比特征的深度差异钝化的剩余层。 在某些实施例中,剩余层在特征开口附近比在特征内更加钝化。 该方法可以继续在剩余层上沉积相同或其它材料的附加层。 由于剩余层的差分钝化,在该后续沉积操作期间的沉积速率在特征开口附近比在特征内部的沉积速率更慢。 这种沉积变化又可以有助于防止特征的过早闭合并且有助于以基本无空隙的方式填充特征。
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公开(公告)号:US20190206731A1
公开(公告)日:2019-07-04
申请号:US16294736
申请日:2019-03-06
发明人: Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号: H01L21/768 , C23C16/06 , C23C16/04 , H01L21/285 , H01L21/321 , H01L27/108
CPC分类号: H01L21/76879 , C23C16/04 , C23C16/045 , C23C16/06 , H01L21/28556 , H01L21/321 , H01L21/76898 , H01L27/10891
摘要: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
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公开(公告)号:US10103058B2
公开(公告)日:2018-10-16
申请号:US15482271
申请日:2017-04-07
发明人: Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号: H01L21/4763 , H01L21/768 , H01L21/3213 , C23C16/04 , H01L27/108 , H01L27/105 , H01L21/285 , H01L21/321
摘要: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
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公开(公告)号:US20140134827A1
公开(公告)日:2014-05-15
申请号:US14074596
申请日:2013-11-07
发明人: Shankar Swaminathan , Bart van Schravendijk , Adrien Lavoie , Sesha Varadarajan , Jason Daejin Park , Michal Danek , Naohiro Shoda
IPC分类号: H01L21/762 , H01L21/67
CPC分类号: H01L21/76224 , C23C16/045 , C23C16/45523 , C23C16/56 , H01L21/02126 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/67017
摘要: A method and apparatus for conformally depositing a dielectric oxide in high aspect ratio gaps in a substrate is disclosed. A substrate is provided with one or more gaps into a reaction chamber where each gap has a depth to width aspect ratio of greater than about 5:1. A first dielectric oxide layer is deposited in the one or more gaps by CFD. A portion of the first dielectric oxide layer is etched using a plasma etch, where etching the portion of the first dielectric oxide layer occurs at a faster rate near a top surface than near a bottom surface of each gap so that the first dielectric oxide layer has a tapered profile from the top surface to the bottom surface of each gap. A second dielectric oxide layer is deposited in the one or more gaps over the first dielectric oxide layer via CFD.
摘要翻译: 公开了一种用于在衬底中的高纵横比间隙中共形沉积介电氧化物的方法和装置。 衬底在反应室中具有一个或多个间隙,其中每个间隙具有大于约5:1的深宽比。 第一电介质氧化物层通过CFD沉积在一个或多个间隙中。 使用等离子体蚀刻蚀刻第一电介质氧化物层的一部分,其中蚀刻第一电介质氧化物层的部分以比在每个间隙的底表面附近的顶表面附近以更快的速率发生,使得第一电介质氧化物层具有 从每个间隙的顶表面到底表面的锥形轮廓。 第二电介质氧化物层通过CFD沉积在第一电介质氧化物层上的一个或多个间隙中。
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10.
公开(公告)号:US09673146B2
公开(公告)日:2017-06-06
申请号:US14989444
申请日:2016-01-06
发明人: Feng Chen , Raashina Humayun , Michal Danek , Anand Chandrashekar
IPC分类号: H01L21/44 , H01L23/535 , C23C16/02 , C23C16/04 , C23C16/14 , C23C16/455 , H01L21/285 , H01L21/768 , H01L21/67 , C23C16/52 , H01L23/532
CPC分类号: H01L23/535 , C23C16/0272 , C23C16/045 , C23C16/14 , C23C16/45523 , C23C16/52 , H01L21/28556 , H01L21/67017 , H01L21/76816 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L21/76879 , H01L21/76895 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.
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