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公开(公告)号：US20210151251A1
公开(公告)日：2021-05-20
申请号：US16689347
申请日：2019-11-20
Applicant: NXP B.V.
Inventor： Chayathorn Saklang , Wiwat Tanwongwan , Amornthep Saiyajitara , Chanon Suwankasab
Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.
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公开(公告)号：US20230178457A1
公开(公告)日：2023-06-08
申请号：US17643193
申请日：2021-12-08
Applicant: NXP B.V.
IPC: H01L23/495 , H01L23/31 , H01L23/00
CPC classification number: H01L23/49503 , H01L23/49593 , H01L23/3107 , H01L24/32 , H01L24/29 , H01L24/83 , H01L2224/32245 , H01L2224/2919 , H01L2224/83385 , H01L24/48 , H01L2224/48245 , H01L24/73 , H01L2224/73265
Abstract: A semiconductor package comprises a leadframe, a component module, and a semiconductor die. The leadframe has a plurality of insertion terminals, a split die pad, and one or more leads. The component module has one or more passive components mounted on a substrate. The semiconductor die has an integrated circuit. The component module is mounted on a split die pad at a first surface of the leadframe and forms an electrical connection with the insertion terminals. Further, the semiconductor die is mounted on the split die pad at a second surface of the leadframe which is opposite to the first surface.
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公开(公告)号：US11114239B2
公开(公告)日：2021-09-07
申请号：US16689347
申请日：2019-11-20
Applicant: NXP B.V.
Inventor： Chayathorn Saklang , Wiwat Tanwongwan , Amornthep Saiyajitara , Chanon Suwankasab
Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.
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公开(公告)号：US20200273810A1
公开(公告)日：2020-08-27
申请号：US16283853
申请日：2019-02-25
Applicant: NXP B.V.
Inventor： Chayathorn Saklang , Amomthep Saiyaitara , Chanon Suwankasab , Russell Joseph Lynch
IPC: H01L23/552 , H01L23/06 , H01L23/29 , H01L23/31 , H01L23/528 , H01L23/49 , H01L23/495
Abstract: A shielded semiconductor device has a first die attached to a die pad of a lead frame and a second die attached to a surface of the first die. The first die is electrically connected to inner lead ends of leads that surround the die pad, and the second die is electrically connected to the first die and to an inner end of a shielding lead. A mold compound forms a body around the first and second dies and the electrical connections. Outer lead ends of the leads project from the sides of the body. The outer end of the shielding lead projects from a central location of one side of the body and is bent up the side surface from which it projects and over the top of the body and provides EMI shielding.
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公开(公告)号：US20170133342A1
公开(公告)日：2017-05-11
申请号：US15339594
申请日：2016-10-31
Applicant: NXP B.V.
Inventor： Wiwat Tanwongwan , Piyarat Suwannakha , Chanon Suwankasab
IPC: H01L23/00 , H01L21/56 , H01L21/48 , H01L23/495 , H01L23/31
CPC classification number: H01L24/48 , H01L21/4825 , H01L21/565 , H01L23/3114 , H01L23/49503 , H01L23/4952 , H01L23/49541 , H01L24/85 , H01L2224/32245 , H01L2224/48095 , H01L2224/48245 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/73265 , H01L2224/85047 , H01L2224/85181 , H01L2224/85205 , H01L2924/00014 , H01L2924/181 , H01L2924/3512 , H01L2924/386 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399 , H01L2924/00
Abstract: An integrated circuit package is provided. The integrated circuit package comprises: a die; a lead; and a bond wire comprising a first end coupled to the die and a second end coupled to the lead via bond. The bond wire further comprises: a first portion between a first bend in the bond wire and the bond and forming a first angle with respect to the lead; and a second portion forming a second angle with respect to the lead. The first bend is immediately between the first and second portions and is configured to reduce the angle of the bond wire with respect to the lead from the second angle to the first angle.
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Patent Agency Ranking
公开(公告)号：US12125771B2
公开(公告)日：2024-10-22
申请号：US17643193
申请日：2021-12-08
Applicant: NXP B.V.
IPC: H01L23/495 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49503 , H01L23/3107 , H01L23/49593 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/48 , H01L24/73 , H01L2224/2919 , H01L2224/32245 , H01L2224/48245 , H01L2224/73265 , H01L2224/83385
Abstract: A semiconductor package comprises a leadframe, a component module, and a semiconductor die. The leadframe has a plurality of insertion terminals, a split die pad, and one or more leads. The component module has one or more passive components mounted on a substrate. The semiconductor die has an integrated circuit. The component module is mounted on a split die pad at a first surface of the leadframe and forms an electrical connection with the insertion terminals. Further, the semiconductor die is mounted on the split die pad at a second surface of the leadframe which is opposite to the first surface.
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公开(公告)号：US11049817B2
公开(公告)日：2021-06-29
申请号：US16283853
申请日：2019-02-25
Applicant: NXP B.V.
Inventor： Chayathorn Saklang , Amornthep Saiyajitara , Chanon Suwankasab , Russell Joseph Lynch
IPC: H01L23/552 , H01L23/06 , H01L23/29 , H01L23/31 , H01L23/495 , H01L23/49 , H01L23/528
Abstract: A shielded semiconductor device has a first die attached to a die pad of a lead frame and a second die attached to a surface of the first die. The first die is electrically connected to inner lead ends of leads that surround the die pad, and the second die is electrically connected to the first die and to an inner end of a shielding lead. A mold compound forms a body around the first and second dies and the electrical connections. Outer lead ends of the leads project from the sides of the body. The outer end of the shielding lead projects from a central location of one side of the body and is bent up the side surface from which it projects and over the top of the body and provides EMI shielding.
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公开(公告)号：US10790220B2
公开(公告)日：2020-09-29
申请号：US16164776
申请日：2018-10-18
Applicant: NXP B.V.
Inventor： Chayathorn Saklang , Stephen Ryan Hooper , Chanon Suwankasab , Amornthep Saiyajitara , Bernd Offermann , James Lee Grothe , Russell Joseph Lynch
IPC: H01L23/495 , H01L23/31 , H01L21/56 , H01R12/58
Abstract: A press-fit semiconductor device includes a lead frame having a die pad, leads with inner and outer lead ends, and a press-fit lead. The press-fit lead has a circular section between an outer lead end and an inner lead end, and the circular section has a central hole that is sized and shaped to receive a press-fit connection pin. A die is attached to the die pad and electrically connected to the inner lead ends of the leads and the inner lead end of the press-fit lead. The die, electrical connections and inner lead ends are covered with an encapsulant that forms a housing. The outer lead ends of the leads extend beyond the housing. The housing has a hole extending therethrough that is aligned with the center hole of the press-fit lead, so that a press-fit connection pin can be pushed through the hole to connect the device to a circuit board.
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公开(公告)号：US10340211B1
公开(公告)日：2019-07-02
申请号：US15922873
申请日：2018-03-15
Applicant: NXP B.V.
Inventor： Chanon Suwankasab , Amornthep Saiyajitara , Chayathorn Saklang , Stephen Ryan Hooper
IPC: H01L23/495 , H01L21/56 , G01P1/02 , H01L25/16 , H01L23/31 , H01L23/00 , H01L25/00 , H01L23/02 , H01L21/52 , G01P15/00
Abstract: A sensor module, such as an acceleration sensor module, includes a leaded socket assembly covered by a housing. The leaded socket assembly includes a dual gauge lead frame, a sensor die, and various passive devices. The sensor die and the passive devices are mounted on the lead frame, and then the lead frame, sensor die, and passive devices are over-molded to form the leaded socket assembly. Neither the sensor module nor the socket assembly includes a printed circuit board, so many conventional sensor module assembly steps are bypassed.
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公开(公告)号：US09257374B1
公开(公告)日：2016-02-09
申请号：US14582521
申请日：2014-12-24
Applicant: NXP B.V.
Inventor： Chanon Suwankasab , Amornthep Saiyajiatara
IPC: H01L23/495 , H01L23/31 , H01L23/00
CPC classification number: H01L23/49555 , H01L23/3107 , H01L23/49582 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/94 , H01L2224/2919 , H01L2224/32245 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/73265 , H01L2224/83101 , H01L2224/83191 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83464 , H01L2224/83856 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85464 , H01L2224/92247 , H01L2224/94 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2224/27 , H01L2924/00014 , H01L2924/0665 , H01L2924/00012
Abstract: Consistent with an example embodiment, a thin outline shrink package (TSOP) provides for a significant reduction in lead pitch along with a reduced package profile for a semiconductor device die packaged, therein.
Abstract translation: 与示例性实施例一致，薄外形收缩封装（TSOP）提供了引线间距的显着降低以及其中封装的半导体器件封装的减小的封装形状。
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