公开(公告)号：US20180226353A1

公开(公告)日：2018-08-09

申请号：US15427010

申请日：2017-02-07

Applicant: NXP B.V.

Inventor： Ekapong Tangpattanasaeree ,  Wiwat Tanwongwan ,  Amornthep Saiyajitara

IPC: H01L23/544 ,  H01L21/48 ,  H01L23/495

CPC classification number: H01L23/544 ,  H01L23/495 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54486

Abstract: A lead frame used in semiconductor device assembly includes first and second opposing planar surfaces. A marking area is defined on the first planar surface. The marking area has a uniform background color that is different from a color of the first planar surface. A mark is formed in the marking area. The background color of the marking area contrasts with a color of the mark such that a clear image of the mark is easily captured with an image sensor. The mark preferably is a two-dimensional (2D) mark made of bumps and represents encoded information. The contrast between the background color and the mark is especially helpful when the lead frame has a roughened surface.

公开(公告)号：US20210151251A1

公开(公告)日：2021-05-20

申请号：US16689347

申请日：2019-11-20

Applicant: NXP B.V.

Inventor： Chayathorn Saklang ,  Wiwat Tanwongwan ,  Amornthep Saiyajitara ,  Chanon Suwankasab

IPC: H01G2/06 ,  H05K3/34 ,  H01L23/00

Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.

公开(公告)号：US20210035820A1

公开(公告)日：2021-02-04

申请号：US17072569

申请日：2020-10-16

Applicant: NXP B.V.

Inventor： Wiwat Tanwongwan ,  Amornthep Saiyajitara ,  Nathapop Lappanitpullpol

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  G06K19/077 ,  H01L23/498 ,  H01L21/48

Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

公开(公告)号：US20200258831A1

公开(公告)日：2020-08-13

申请号：US16270607

申请日：2019-02-08

Applicant: NXP B.V.

Inventor： Amornthep Saiyajitara ,  Wiwat Tanwongwan ,  Nathapop Lappanitpullpol

IPC: H01L23/498 ,  H01L23/00

Abstract: A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.

公开(公告)号：US20230178457A1

公开(公告)日：2023-06-08

申请号：US17643193

申请日：2021-12-08

Applicant: NXP B.V.

Inventor： Chayathorn Saklang ,  Chanon Suwankasab ,  Amornthep Saiyajitara ,  Verapath Vareesantichai

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L23/49593 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/2919 ,  H01L2224/83385 ,  H01L24/48 ,  H01L2224/48245 ,  H01L24/73 ,  H01L2224/73265

Abstract: A semiconductor package comprises a leadframe, a component module, and a semiconductor die. The leadframe has a plurality of insertion terminals, a split die pad, and one or more leads. The component module has one or more passive components mounted on a substrate. The semiconductor die has an integrated circuit. The component module is mounted on a split die pad at a first surface of the leadframe and forms an electrical connection with the insertion terminals. Further, the semiconductor die is mounted on the split die pad at a second surface of the leadframe which is opposite to the first surface.

公开(公告)号：US11114239B2

公开(公告)日：2021-09-07

申请号：US16689347

申请日：2019-11-20

Applicant: NXP B.V.

Inventor： Chayathorn Saklang ,  Wiwat Tanwongwan ,  Amornthep Saiyajitara ,  Chanon Suwankasab

IPC: H01G2/06 ,  H01L23/00 ,  H05K3/34

Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.

公开(公告)号：US10249556B1

公开(公告)日：2019-04-02

申请号：US15913855

申请日：2018-03-06

Applicant: NXP B.V.

Inventor： Verapath Vareesantichai ,  Amornthep Saiyajitara ,  Pimpa Boonyatee ,  Adrianus Buijsman

IPC: H01L23/495 ,  H01L23/482

Abstract: A lead frame strip includes an array of lead frames. The lead frames each include a die pad and lead fingers that are spaced from the die pads and disposed along one or more sides of the die pads. The lead fingers have proximal ends near to the die pad and distal ends farther from the die pad. Connection bars extend between the lead frames. The lead fingers of adjacent lead frames extend from opposing sides of the connection bars. The connection bars have first portions where the lead fingers are connected thereto, and second portions between adjacent lead finger connections to the connection bar. The second portions are etched to form a bar that extends diagonally from a first one of the adjacent lead fingers connected thereto to a second one of the adjacent lead fingers connected thereto.

公开(公告)号：US11482478B2

公开(公告)日：2022-10-25

申请号：US16936480

申请日：2020-07-23

Applicant: NXP B.V.

Inventor： Crispulo Estira Lictao, Jr. ,  Chayathorn Saklang ,  Amornthep Saiyajitara ,  Chanon Suwankasab ,  Stephen Ryan Hooper ,  Bernd Offermann

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/00 ,  H01L25/00

Abstract: An electronic device package includes a first die coupled to a substrate, a second die coupled with the first die, and a spacer element coupled to the second die to form a stacked structure that includes the first die, the second die, and the spacer element. An electrically conductive shield overlies the stacked structure. The shield has a first end coupled to the spacer element and a second end coupled to the substrate. Inter-chip bond wires may electrically interconnect the first and second dies, and the shield may additionally overlie the bond wires. The spacer element may extend above a surface of the second die at a height that is sufficient to prevent the shield from touching the inter-chip bond wires.

公开(公告)号：US20220028766A1

公开(公告)日：2022-01-27

申请号：US16936480

申请日：2020-07-23

Applicant: NXP B.V.

Inventor： Crispulo Estira Lictao, JR. ,  Chayathorn Saklang ,  Amornthep Saiyajitara ,  Chanon Suwankasab ,  Stephen Ryan Hooper ,  Bernd Offermann

IPC: H01L23/495 ,  H01L23/552 ,  H01L23/00 ,  H01L25/00

Abstract: An electronic device package includes a first die coupled to a substrate, a second die coupled with the first die, and a spacer element coupled to the second die to form a stacked structure that includes the first die, the second die, and the spacer element. An electrically conductive shield overlies the stacked structure. The shield has a first end coupled to the spacer element and a second end coupled to the substrate. Inter-chip bond wires may electrically interconnect the first and second dies, and the shield may additionally overlie the bond wires. The spacer element may extend above a surface of the second die at a height that is sufficient to prevent the shield from touching the inter-chip bond wires.

公开(公告)号：US20200126895A1

公开(公告)日：2020-04-23

申请号：US16164776

申请日：2018-10-18

Applicant: NXP B.V.

Inventor： Chayathorn Saklang ,  Stephen Ryan Hooper ,  Chanon Suwankasab ,  Amornthep Saiyajitara ,  Bernd Offermann ,  James Lee Grothe ,  Russell Joseph Lynch

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A press-fit semiconductor device includes a lead frame having a die pad, leads with inner and outer lead ends, and a press-fit lead. The press-fit lead has a circular section between an outer lead end and an inner lead end, and the circular section has a central hole that is sized and shaped to receive a press-fit connection pin. A die is attached to the die pad and electrically connected to the inner lead ends of the leads and the inner lead end of the press-fit lead. The die, electrical connections and inner lead ends are covered with an encapsulant that forms a housing. The outer lead ends of the leads extend beyond the housing. The housing has a hole extending therethrough that is aligned with the center hole of the press-fit lead, so that a press-fit connection pin can be pushed through the hole to connect the device to a circuit board.