公开(公告)号：US20210035820A1

公开(公告)日：2021-02-04

申请号：US17072569

申请日：2020-10-16

Applicant: NXP B.V.

Inventor： Wiwat Tanwongwan ,  Amornthep Saiyajitara ,  Nathapop Lappanitpullpol

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  G06K19/077 ,  H01L23/498 ,  H01L21/48

Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

公开(公告)号：US20200258831A1

公开(公告)日：2020-08-13

申请号：US16270607

申请日：2019-02-08

Applicant: NXP B.V.

Inventor： Amornthep Saiyajitara ,  Wiwat Tanwongwan ,  Nathapop Lappanitpullpol

IPC: H01L23/498 ,  H01L23/00

Abstract: A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.

公开(公告)号：US11637024B2

公开(公告)日：2023-04-25

申请号：US17072569

申请日：2020-10-16

Applicant: NXP B.V.

Inventor： Wiwat Tanwongwan ,  Amornthep Saiyajitara ,  Nathapop Lappanitpullpol

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  G06K19/077 ,  H01L23/498 ,  H01L21/48

Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

公开(公告)号：US10763203B1

公开(公告)日：2020-09-01

申请号：US16270607

申请日：2019-02-08

Applicant: NXP B.V.

Inventor： Amornthep Saiyajitara ,  Wiwat Tanwongwan ,  Nathapop Lappanitpullpol

IPC: H01L23/498 ,  H01L23/00

Abstract: A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.