公开(公告)号：US11677008B2

公开(公告)日：2023-06-13

申请号：US17534799

申请日：2021-11-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ching-Chia Huang ,  Tseng-Fu Lu

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H10B12/00

CPC分类号： H01L29/4236 ,  H01L21/823456 ,  H01L27/088 ,  H10B12/34 ,  H10B12/488

摘要： The present disclosure provides a method for preparing a semiconductor device with a T-shaped buried gate electrode. The method includes forming an isolation structure in a semiconductor substrate to define an active region, and forming a doped region in the active region. The method also includes etching the semiconductor substrate to form a first trench and a second trench. The first trench has a first portion extending across the doped region and a second portion extending away from the first portion, and the second trench has a third portion extending across the doped region and a fourth portion extending away from the third portion. The method further includes forming a first gate electrode in the first trench and a second gate electrode in the second trench.

公开(公告)号：US11848353B2

公开(公告)日：2023-12-19

申请号：US17643404

申请日：2021-12-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ching-Chia Huang ,  Tseng-Fu Lu

IPC分类号： H01L21/762 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H10B12/00 ,  H01L29/66

CPC分类号： H01L29/0607 ,  H01L21/76237 ,  H01L29/4236 ,  H01L29/7813 ,  H01L29/7825 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851 ,  H10B12/053

摘要： A method includes forming a semiconductor layer on a semiconductor substrate. The semiconductor layer is patterned to form a semiconductive structure. Each of widths of two ends of the semiconductive structure is wider than a width of a middle of the semiconductive structure. The semiconductive structure is doped to form a doped semiconductor structure. An isolation structure is formed to surround the doped semiconductor structure. A recessing process is performed such that two trenches are formed on the doped semiconductor structure, and first, second and third portions of an active region are formed on the semiconductor substrate. A first gate structure and a second gate structure are formed in the trenches such that the first portion and the third portion are partially spaced apart by the first gate structure, and the second portion and the third portion are partially spaced apart by the second gate structure.

公开(公告)号：US11818876B2

公开(公告)日：2023-11-14

申请号：US17563286

申请日：2021-12-28

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tseng-Fu Lu

IPC分类号： H10B12/00 ,  G11C5/06

CPC分类号： H10B12/0335 ,  G11C5/063 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/488

摘要： The present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate comprising one or more isolation features defining active regions; forming at least one access transistor comprising a plurality of impurity regions, wherein the impurity regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated impurity region; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first and second contact holes.

公开(公告)号：US11605718B2

公开(公告)日：2023-03-14

申请号：US17526125

申请日：2021-11-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tseng-Fu Lu

IPC分类号： H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L27/108

摘要： The present disclosure provides a method for preparing a semiconductor structure. The method includes providing a substrate comprising a first top surface; forming an isolation region in the substrate to surround an active region; implanting a plurality of dopants into the substrate to form a first impurity region, a second impurity region and a third impurity region in the active region; forming a gate trench in the active region; forming a first barrier layer on a portion of a sidewall of the gate trench; forming a first gate material in the gate trench, wherein the first gate material comprises a first member surrounded by the first barrier layer; forming a second barrier layer on the first barrier layer and the first gate material; forming a second gate material on the second barrier layer; and forming a gate insulating material on the second gate material.

公开(公告)号：US11315928B2

公开(公告)日：2022-04-26

申请号：US17014282

申请日：2020-09-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chiang-Lin Shih ,  Tseng-Fu Lu ,  Jeng-Ping Lin

IPC分类号： H01L27/108 ,  H01L23/535 ,  H01L21/74

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate having a first top surface. An active region is surrounded by an isolation region in the substrate. A buried power line and a buried signal line are disposed within the substrate and in the active region. A first circuit layer is disposed on the first top surface of the substrate to cover the buried power line and the buried signal line. A second circuit layer is disposed on the first top surface of the substrate and separated from the first circuit layer. A cell capacitor is disposed on and electrically coupled to the first circuit layer.

公开(公告)号：US12063771B2

公开(公告)日：2024-08-13

申请号：US17651068

申请日：2022-02-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tseng-Fu Lu ,  Chuan-Lin Hsiao

IPC分类号： H10B12/00 ,  H01L21/762 ,  H01L29/06

CPC分类号： H10B12/315 ,  H01L21/762 ,  H01L29/0649 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

摘要： A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric confomally formed on the first groove and the first slot.

公开(公告)号：US11094692B2

公开(公告)日：2021-08-17

申请号：US16683229

申请日：2019-11-13

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ching-Chia Huang ,  Tseng-Fu Lu

IPC分类号： H01L27/088 ,  H01L27/108 ,  H01L29/36 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8234

摘要： A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure.

公开(公告)号：US11037921B2

公开(公告)日：2021-06-15

申请号：US16653979

申请日：2019-10-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Fang-Wen Liu ,  Tseng-Fu Lu

IPC分类号： H01L27/02 ,  H01L27/07

摘要： An off chip driver structure includes a plurality of pull-up transistors, a plurality of pull-down transistors, a plurality of first regions of a first type, a plurality of second regions of a second type and a plurality of resistor components. The first regions and the second regions are staggered to form an electrostatic discharge (ESD) component. One of the resistor components is coupled to one of the pull-up transistors or one of the pull-down transistors, the resistor components are arranged between the first regions and the second regions.

公开(公告)号：US10825898B2

公开(公告)日：2020-11-03

申请号：US16720796

申请日：2019-12-19

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Jhen-Yu Tsai ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06

摘要： The semiconductor layout structure includes an active region surrounded by an isolation structure, at least one first gate structure disposed over the active region and the isolation structure, at least one second gate structure disposed over the active region and the isolation structure, and a plurality of source/drain regions disposed in the active region. The active region includes two first regions, a second region disposed between the two first regions, a third region disposed between one of the first region and the second region, and a fourth region disposed between the other first region and the second region.

公开(公告)号：US10242978B1

公开(公告)日：2019-03-26

申请号：US15794834

申请日：2017-10-26

申请人： Nanya Technology Corporation

发明人： Fang-Wen Liu ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC分类号： H01L27/02 ,  H01L49/02

摘要： The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.